Memory-efficient turbo decoder architectures for LDPC codes

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn 2002-January, Issue , 2002, Pages 159-164

  Mansour, M M ^a   Shanbhag, N R ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Bit error rate; Concatenated codes; Convergence; Convolutional codes; Electronic mail; Iterative decoding; Memory architecture; Parity check codes; Throughput; Turbo codes

Indexed keywords

ALGORITHMS; BIT ERROR RATE; CONCATENATED CODES; CONVOLUTIONAL CODES; ELECTRONIC MAIL; ERROR CORRECTION; FORWARD ERROR CORRECTION; ITERATIVE DECODING; ITERATIVE METHODS; MATRIX ALGEBRA; MEMORY ARCHITECTURE; MESSAGE PASSING; SATELLITE COMMUNICATION SYSTEMS; SIGNAL PROCESSING; THROUGHPUT; TURBO CODES;

CONVERGENCE; DECODER ARCHITECTURE; IRREGULAR LOW-DENSITY PARITY-CHECK CODES; MESSAGE PASSING ALGORITHM; NUMBER OF ITERATIONS; PARITY CHECK CODES; PARITY CHECK MATRICES; REDUCED MEMORY REQUIREMENTS;

CODES (SYMBOLS);

EID: 84948982039     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2002.1049702     Document Type: Conference Paper

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