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Volumn 48, Issue 4, 2004, Pages 617-625

An effective model for analysing tunneling gate leakage currents through ultrathin oxides and high-k gate stacks from Si inversion layers

Author keywords

Gate dielectric scalability; High k dielectrics; Inversion layer; Quasibound state lifetime; Tunneling current

Indexed keywords

DIELECTRIC MATERIALS; ELECTRON TUNNELING; INTERFACES (MATERIALS); LEAKAGE CURRENTS; OXIDES; PERMITTIVITY;

EID: 0442311955     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2003.09.031     Document Type: Conference Paper
Times cited : (28)

References (25)
  • 5
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    • Cassan E. J. Appl. Phys. 87(11):2000;7931-7939.
    • (2000) J. Appl. Phys. , vol.87 , Issue.11 , pp. 7931-7939
    • Cassan, E.1
  • 18
    • 0442299305 scopus 로고    scopus 로고
    • Berkeley Univ., http://www-device.eecs.berkeley.edu/.
  • 24
    • 0001156050 scopus 로고
    • Stern H. Phys Rev B. 5(12):1972;4891-4899.
    • (1972) Phys Rev B , vol.5 , Issue.12 , pp. 4891-4899
    • Stern, H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.