Optimization and realization of sub-100-nm channel length single halo p-MOSFETs

IEEE Transactions on Electron Devices

Volumn 49, Issue 6, 2002, Pages 1077-1079

  Borse, D G ^a   Manjula Rani, K N ^a   Jha, Neeraj K ^a   Chandorkar, A N ^a   Vasi, J ^a   Ramgopal Rao, V ^a   Cheng, B ^b   Woo, J C S ^c  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b Advanced Process Development and External Research   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Asymmetric channel; Charge pumping; Halo doping; Hot carrier; LAC; MOSFET optimization; p MOSFET

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC FIELDS; FABRICATION; HOT CARRIERS; OPTIMIZATION; SEMICONDUCTOR DOPING; TRANSCONDUCTANCE;

ASYMMETRIC CHANNELS;

MOSFET DEVICES;

EID: 0036610054     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2002.1003752     Document Type: Article

References (9)

1. A new asymmetrical halo source GOLD drain (HS-GOLD) sub half micrometer n-MOSFET design for reliability and performance
2. Using focused ion beam to optimize sub micron MOSFET characteristics
3. A low voltage graded-channel MOSFET (LV-GCMOS) for sub 1-volt microcontroller application
4. Realization of sub 100nm asymmetric channel MOSFETs with excellent short channel performance and reliability
5. Channel engineering for high speed Sub-1.0 V power supply deep sub-micron CMOS
6. A study of 100nm channel length asymmetric MOSFETs by using charge pumping
7. Exploration of velocity overshoot in a high-performance deep sub 100 nm SOI MOSFET with asymmetric channel profile
8. A study of 100nm channel length asymmetric MOSFETs by using charge pumping