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Volumn 3212, Issue , 1997, Pages 42-51

Surface preparation, growth and characterization of ultrathin gate oxides for scaled CMOS applications

Author keywords

[No Author keywords available]

Indexed keywords

B DIFFUSIONS; BAND GAPS; BORON PENETRATIONS; CMOS SCALING; DEPLETION EFFECTS; DEVICE OPERATIONS; DIELECTRIC CONSTANTS; DIRECT TUNNELING CURRENTS; ELECTRICAL BEHAVIORS; ELECTRICAL PROPERTIES; ELECTRICAL THICKNESSES; ELECTRON EFFECTIVE MASSES; FUNDAMENTAL PARAMETERS; GATE DIELECTRIC MATERIALS; GATE OXIDE THICKNESSES; GATE OXIDES; INTERFACE QUALITIES; INTERFACE ROUGHNESSES; OXIDE THICKNESSES; PHYSICAL AND ELECTRICAL CHARACTERIZATIONS; PINHOLE FORMATIONS; PREPARATION TECHNIQUES; REPRODUCIBILITY; SACRIFICIAL OXIDES; SURFACE PREPARATIONS; TERMINATED SURFACES; TUNNELING CURRENTS; ULTRATHIN OXIDES;

EID: 0345909576     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.284618     Document Type: Conference Paper
Times cited : (7)

References (53)
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    • 2 Interface, edited by C.R. Helms and B.E. Deal (Plenum, New York, 1988).
    • (1988) 2 Interface
    • Maserjian, J.1
  • 35
    • 57649145107 scopus 로고    scopus 로고
    • private communication
    • S. Tang, private communication.
    • Tang, S.1
  • 38
    • 57649169592 scopus 로고    scopus 로고
    • to be published
    • Z.H. Lu et al., to be published.
    • Lu, Z.H.1
  • 46
    • 0030655686 scopus 로고    scopus 로고
    • VLSI Tech
    • D.T. Grider et al., VLSI Tech. Symp. Dig., p. 47 (1997).
    • (1997) Symp. Dig , pp. 47
    • Grider, D.T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.