Application of high pressure deuterium annealing for improving the hot carrier reliability of CMOS transistors

IEEE Electron Device Letters

Volumn 21, Issue 5, 2000, Pages 221-223

  Jinju, Lee ^a   Cheng, Kangguo ^a   Chen, Zhi ^a   Hess, Karl ^a   Lyding, Joseph W ^a   Young Kwang, Kim ^b   Seung, Lee ^b   Young Wug, Kim ^b   Kwang Pyuk, Suh ^b  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; DEUTERIUM; HIGH PRESSURE EFFECTS; HOT CARRIERS; INTERFACES (MATERIALS); RELIABILITY; SECONDARY ION MASS SPECTROMETRY; SEMICONDUCTING SILICON; SILICA; SILICON WAFERS;

DIFFUSION BARRIER; GAS ANNEAL; NITRIDE SIDEWALL SPACERS;

MOSFET DEVICES;

EID: 0343353848     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.841302     Document Type: Article

References (12)

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