On the mechanism for interface trap generation in MOS transistors due to channel hot carrier stressing

IEEE Electron Device Letters

Volumn 21, Issue 1, 2000, Pages 24-26

  Chen, Zhi ^a,b   Hess, Karl ^a   Lee, Jinju ^a   Lyding, Joseph W ^a   Rosenbaum, Elyze ^a   Kizilyalli, Isik ^c   Chetlur, Sundar ^c   Huang, Robert ^c  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b UNIVERSITY OF KENTUCKY   (United States)

^c NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEUTERIUM; GATES (TRANSISTOR); HOLE TRAPS; HOT CARRIERS; INTERFACES (MATERIALS);

INTERFACE TRAP GENERATION;

MOSFET DEVICES;

EID: 0033887302     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.817441     Document Type: Article

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