The effect of deuterium passivation at different steps of cmos processing on lifetime improvements of cmos transistors

IEEE Transactions on Electron Devices

Volumn 46, Issue 8, 1999, Pages 1812-1813

  Lee, Jinju ^a   Epstein, Yefim ^a   Berti, Antonio C ^a   Huber, John ^a   Hess, Karl ^a   Lyding, Joseph W ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

CMOS; Deuterium; Hot carrier; Reliability

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; DEUTERIUM; HOT CARRIERS; INTERFACES (MATERIALS); MOSFET DEVICES; RELIABILITY; SECONDARY ION MASS SPECTROMETRY; SEMICONDUCTING SILICON; SILICA; SINTERING;

DEPTH PROFILE; RELIABILITY LIFETIME IMPROVEMENT;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0033169510     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.777177     Document Type: Article

References (5)

1. J. W. Lyding, K. Hess, and I. C. Kizilyalli, "Reduction of hot electron degradation in MOS transistors by deuterium sintering," Appl. Phys. Lett., vol. 68, p. 2526, 1996
2. I. C. Kizilyalli, J. W. Lyding, and K. Hess, "Deuterium post-metal annealing of MOSFET's for improved hot-carrier reliability," IEEE Electron Device Lett., vol. 18, p. 81, Mar. 1997
3. R. A. Devine, J. L. Autran, W. L. Warren, K. L. Vanheusdan, and J. C. Rostaing, "Interfacial hardness enhancement in deuterium annealed 0.25 \im channel metal oxide semiconductor transistors," Appl. Phys. Lett., vol. 70, p. 2999, 1997
4. J. Lee, S. Aur, R. Eklund, K. Hess, and J. W. Lyding, "SIMS character- ization of the deuterium sintering process for enhanced-lifetime CMOS transistors," J. Vac. Sci. Technol, vol. A16, p. 1762, 1998
5. J. Lee, J. Baker, R. Wilson, and J. W. Lyding, "SIMS depth profiles of H and 2 H at the SiC>2/Si interface of deuterium-sintered CMOS devices," in Proc. SIMS XI, 1997, pp. 205-208.