Test limitations of parametric faults in analog circuits

IEEE Transactions on Instrumentation and Measurement

Volumn 52, Issue 5, 2003, Pages 1444-1454

  Savir, Jacob ^a   Guo, Zhen ^a  

^a NEW JERSEY INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Analog circuit specifications; Fault detection; Fault masking; Monte Carlo simulation; Parameter drift; Parameter sensitivity

Indexed keywords

COMPUTER SIMULATION; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; MONTE CARLO METHODS; OPTIMIZATION; SPECIFICATIONS; TRANSFER FUNCTIONS;

ANALOG CIRCUIT SPECIFICATIONS; FAULT DETECTION; FAULT MASKING; PARAMETER DRIFT;

LINEAR INTEGRATED CIRCUITS;

EID: 0242636484     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2003.818541     Document Type: Article

References (26)

1. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. New York: IEEE Press, 1990.
2. P. H. Bardell, W. H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Techniques. New York: Wiley Interscience, 1987.
3. L. S. Milor, "A tutorial introduction to research on analog and mixed-signal circuit testing," IEEE Trans. Circuits Syst., vol. 45, pp. 1389-1407, Oct. 1998.
4. W. Maly, A. J. Strojwas, and S. W. Director, "VLSI yield prediction and estimation: A unified framework," IEEE Trans. Computer-Aided Design, vol. 5, pp. 114-130, Jan. 1986.
5. C. Michael and M. Ismail, "Statistical modeling of device mismatch for analog MOS integrated circuits," IEEE J. Solid-State Circuits, vol. 27, pp. 154-165, Jan. 1992.
6. W. M. Lindermeir, "Design of Robust test criteria in analog testing," in Proc. ICCAD, 1996, pp. 604-511.
7. ____, "Analog testing by characteristic observation inference," IEEE Trans. Comput.-Aided Design, vol. 18, pp. 1353-1368, Sept. 1999.
8. L. Milor and A. L. Sangiovanni-Vincentelli, "Minimizing production test time to detect faults in analog circuits," IEEE Trans. Computer-Aided Design, vol. 13, pp. 796-813, June 1994.
9. J. B. Brockman and S. W. Director, "Predictive subset testing: Optimizing IC parametric performance for quality, cost, and yield," IEEE Trans. Semicond. Manufact., vol. 2, pp. 104-113, 1989.
10. Z. Wang et al., "Probabilistic fault detection and the selection of measurement for analog integrated circuits," IEEE Trans. Comput-Aided Design, vol. 17, pp. 862-872, Sept. 1998.
11. P. N. Variyam and A. Chatterjee, "Specification-driven test generation for analog circuit," IEEE Trans. Comput.-Aided, Design, vol. 19, pp. 1189-1201, Oct. 2000.
12. S. Sunter and N. Nagi, "Test metrics for analog parametric faults," in Proc. VLSI Test Symp., Apr. 1999, pp. 226-234.
13. A. Abderrahman et al., "Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuit," IEEE Trans. Comput-Aided, Design, vol. 18, no. 3, pp. 332-345, Mar. 1999.
14. N. Nagi and J. A. Abraham, "Hierarchical fault modeling for analog and mixed-signal circuits," in Proc. VLSI Test Symp., 1992, pp. 96-101.
15. K. Saab et al., "Parametric fault simulation and test vector generation," in Proc. Design Automation and Test in Europe, 2000, pp. 650-656.
16. M. K. Iyer and M. L. Bushnell, "Effect of noise on analog circuit testing," J. Electron. Testing: Theory Applicat., vol. 15, pp. 11-22, Mar. 1999.
17. M. Slamani and B. Kaminska, "Fault observability of analog circuits in frequency domain," IEEE Trans. Circuits Syst. II: Analog and Digital Signal Processing, vol. 43, pp. 134-139, Feb. 1996.
18. ____, "Analog circuit fault diagnosis based on sensitivity computational and functional testing," IEEE Design Test Comput., pp. 30-39, 1992.
19. L. Milor and V. Visvanathan, "Detection of catastrophic faults in analog integrated circuits," IEEE Trans. Comput-Aided Design, vol. 8, pp. 114-130, Feb. 1989.
20. C.-T. Chen, Analog and Digital Control System Design: Transfer Function, State-Space, and Algebraic Methods. Philadelphia, PA: Saunders College Publishing, 1993.
21. B. Friedland, Advanced Control System Design. Englewood Cliffs, NJ: Prentice-Hall, 1996.
22. G. Devarayanadurg and M. soma, "Test set selection for structural faults in analog ICs," IEEE Trans. Comput.-Aided Design Integrated Circuits Syst., vol. 18, pp. 1026-1039, July 1999.
23. G. Roberts, "Metrics, techniques, and recent developments in mixed-signal testing," in Proc. ICCAD, 1996, pp. 514-521.
24. G. J. Hemink et al., "Testability analysis of analog systems," IEEE Trans. Comput.-Aided Design, vol. 9, pp. 573-583, June 1990.
25. P. Clayton, Analysis of Linear Circuits. New York: McGraw-Hill, 1989.
26. L. Ljung, System Identification: Theory for the User. Englewood Cliffs, NJ: Prentice-Hall, 1987.