Worst case tolerance analysis and clp-based multifrequency test generation for analog circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 2-3, 1999, Pages 332-345

  Abderrahman, Abdessatar ^a   Cerny, Eduard ^a   Kaminska, Bozena ^a  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

Constraint logic programming (clp); Linear analog circuits; Nonlinear optimisation; Parametric faults; Relational interval arithmetic (ria); Robust tests; Testing

Indexed keywords

CONSTRAINT LOGIC PROGRAMMING (CLP); CONSTRAINT SATISFACTION PROBLEMS (CSP); RELATIONAL INTERVAL ARITHMETIC (RIA);

ALGORITHMS; COMPUTER AIDED LOGIC DESIGN; CONSTRAINT THEORY; DIGITAL ARITHMETIC; LINEAR INTEGRATED CIRCUITS; OPTIMIZATION;

LOGIC PROGRAMMING;

EID: 0033095170     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.748163     Document Type: Article

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