New Systolic Architectures for Inversion and Division in GF(2m)

IEEE Transactions on Computers

Volumn 52, Issue 11, 2003, Pages 1514-1519

  Yan, Zhiyuan ^a   Sarwate, Dilip V ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Division; Extended Euclidean algorithm; Field arithmetic; Finite fields; Inversion; Systolic

Indexed keywords

ALGORITHMS; INFORMATION THEORY; SYSTOLIC ARRAYS;

FINITE FIELDS;

DIGITAL ARITHMETIC;

EID: 0242493804     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (30)

1. R.E. Blahut, Theory and Practice of Error-Control Codes. Reading, Mass.: Addison-Wesley, 1983.
2. W. Diffie and M.E. Hellman, "New Directions in Cryptography," IEEE Trans. Information Theory, vol. 22, pp. 644-654, 1976.
3. D.E. Denning, Cryptography and Data Security, Reading Mass.: Addison-Wesley, 1983.
4. I.S. Reed and T.K. Truong, "The Use of Finite Fields to Compute Convolutions," IEEE Trans. Information Theory, vol. 21, pp. 208-213, Mar. 1975.
5. K.K. Parhi, VLSI Digital Signal Processing Systems. New York: John Wiley & Sons, 1999.
6. K. Araki, I. Fujita, and M. Morisue, "Fast Inverters over Finite Field Based on Euclid's Algorithm," Trans. IEICE, vol. 72E, no. 11, pp. 1230-1234, Nov. 1989.
7. E.D. Mastrovito, "VLSI Architectures for Computations in Galois Fields," PhD thesis, Linköping Univ., 1991.
8. m}," IEEE Trans. Computers, vol. 42, no. 8, pp. 1010-1015, Aug. 1993.
9. C.-T. Huang and C.-W. Wu, "High-Speed C-Testable Systolic Array Design for Galois-Field Inversion," Proc. European Design and Test Conf., pp. 342346, Mar. 1997.
10. m)," IEEE Trans. Computers, vol. 47, no. 10, pp. 1161-1167, Oct: 1998.
11. m)," IEE Proc. Computers and Digital Techniques, pp. 272-278, 1998.
12. m)," Proc. Int'l Symp. Circuits and Systems (ISCAS '94), pp. 203-206, 1994.
13. m)," IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 44, no. 10, pp. 847-855, Oct. 1997.
14. m)," IEEE Trans. Computers, vol. 49, no. 10, pp. 1120-1125, Oct. 2000.
15. E.R. Berlekamp, G. Seroussi, and P. Tong, "A Hypersystolic Reed-Solomon Decoder," Reed-Solomon Codes and Their Applications, S.B. Wicker and V.K. Bhargava, eds., chapter 10, Piscataway, N.J.: IEEE Press, 1994.
16. C. Paar, "Some Remarks on Efficient Inversion in Finite Fields," Proc. 1995 Int'l Symp. Information Theory, 1995.
17. m)," Proc. 1998 Int'l Symp. Information Theory, 1998.
18. m)," IEEE Trans. Computers, vol. 41, no. 8, pp. 972-980, Aug. 1992.
19. m)," IEEE Trans.n Computers, vol. 47, no. 9, pp. 960-970, Sept. 1998.
20. D.V. Sarwate and N.R. Shanbhag, "High-Speed Architectures for ReedSolomon Decoders," IEEE Trans. VLSI Systems, vol. 9, no. 5, pp. 941-955, Oct. 2001.
21. R.P. Brent and H.T. Kung, "Systolic VLSI Arrays for Polynomial GCD Computation," IEEE Trans. Computers, vol. 33, pp. 731-736, 1984.
22. N. Takagi, "A VLSI Algorithm for Modular Division Based on the Binary GCD Algorithm," IEICE Trans. fundamentals of Electronics, Comm., and Computer Sciences, vol. E81-A, no. 5, pp. 724-728, May 1998.
23. m): A High-Speed, Low-Complexity Design," Proc. Int'l Symp. Circuits and Systems (ISCAS '01), pp. 33-36, 2001.
24. m) for Secure Communication, " Proc. Int'l Symp. Circuits and Systems (ISCAS '02), pp. 733-736, 2002.
25. m) Based on Extended Binary GCD Algorithm," IEICE Trans. Fundamentals of Electronics, Comm., and Computer Sciences, vol. E85-A, no. 5, pp. 994-999, May 2002.
26. Z. Yan and D.V. Sarwate, "Systolic Architectures for Finite Field Inversion and Division," Proc. Int'l Symp. Circuits and Systems (ISCAS '02), pp. 789-792, 2002.
27. H.T. Kung, "Why Systolic Architectures?" Computer, vol. 15, no. 1, pp. 37-46, Jan. 1982.
28. E.R. Berlekamp, Algebraic Coding Theory. New York: McGraw-Hill, 1968.
29. H.T. Kung, C.-C. Wang, C.-J. Huang, and K.-C. Tsai, "A 1.00 GHz 0.6-μm 8-Bit Carry Lookahead Adder Using PLA-Styled All-n-Transistor Logic," IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47, pp. 133-135, 2000.
30. C.-C. Wang, P.-M. Lee, R.-C. Lee, and C.-J. Huang, "A 1.25 GHz 32-Bit Tree-Structured Carry Lookahead Adder," Proc. Int'l Symp. Circuits and Systems (ISCAS '01), vol. 4, pp. 80-83, 2001.