A VLSI algorithm for division in GF(2m) based on extended binary GCD algorithm

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E85-A, Issue 5, 2002, Pages 994-999

  Watanabe, Yasuaki ^a   Takagi, Naofumi ^a   Takagi, Kazuyoshi ^a  

^a NAGOYA UNIVERSITY   (Japan)

Author keywords

Division in finite field; Finite field arithmetic; Hardware algorithm; VLSI algorithm

Indexed keywords

CALCULATIONS; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; COUNTING CIRCUITS; DIGITAL ARITHMETIC; INVERSE PROBLEMS; ITERATIVE METHODS; POLYNOMIALS; VECTORS; VLSI CIRCUITS;

BINARY ALGORITHM; FINITE FIELD ARITHMETIC; HARDWARE ALGORITHM; LINEAR ARRAY STRUCTURE;

ALGORITHMS;

EID: 0036579537     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (6)

1. Fast inverters over finite field based on euclid's algorithm
2. m)
3. m)
4. Computational problems associated with Racah algebra
5. A modular inversion hardware algorithm with a redundant binary representation