A 1.0-GHz 0.6-/im 8-bit carry lookahead adder using PLA-styled all-N-transistor logic

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 47, Issue 2, 2000, Pages 133-135

  Wang, Chua Chin ^a   Huang, Chenn Jung ^a   Tsai, Kun Chu ^b  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

^b National Science Council Under

Author keywords

Noninverting block; PLA styled design; Two phase clocking

Indexed keywords

CARRY LOGIC; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; LOGIC CIRCUITS; LOGIC DESIGN; TIMING CIRCUITS; TRANSISTORS;

ALL-N-TRANSISTOR (ANT); CARRY LOOKAHEAD ADDER (CLA); PROGRAMMABLE LOGIC ARRAYS (PLA);

ADDERS;

EID: 0033896703     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.823541     Document Type: Article

References (4)

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