Systolic architectures for finite field inversion and division

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  Yan, Zhiyuan ^a   Sarwate, Dilip V ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; DIGITAL ARITHMETIC; DIVIDING CIRCUITS (ARITHMETIC); LOGIC GATES; POLYNOMIALS; VLSI CIRCUITS;

AREA TIME COMPLEXITY; CRITICAL PATH DELAY; FINITE FIELD INVERSION AND DIVISION; LATENCY; MODIFIED EUCLIDEAN ALGORITHM; SYSTOLIC ARCHITECTURES;

SYSTOLIC ARRAYS;

EID: 0036296278     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

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