High-speed C-testable systolic array design for Galois-Field inversion

Proceedings of European Design and Test Conference

Volumn , Issue , 1997, Pages 342-346

  Huang, Chih Tsun ^a   Wu, Cheng Wen ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; PARALLEL ALGORITHMS; PARALLEL PROCESSING SYSTEMS; POLYNOMIALS; SYSTOLIC ARRAYS;

EXTENDED EUCLIDEAN ALGORITHM (XEA); GALOIS FIELD (GF) INVERSION;

VLSI CIRCUITS;

EID: 0030679131     PISSN: 10661409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)