An area-efficient systolic division circuit over GF(2m) for secure communication

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  Wu, Chien Hsing ^a   Wu, Chien Ming ^a   Shieh, Ming Der ^a   Hwang, Yin Tsung ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; CRYPTOGRAPHY; ITERATIVE METHODS; MULTIPLEXING EQUIPMENT; POLYNOMIALS; SECURITY OF DATA; SYSTOLIC ARRAYS; VLSI CIRCUITS;

AREA-TIME COMPLEXITY; ITERATIVE DIVISION ALGORITHM; PARALLEL-IN PARALLEL-OUT SYSTOLIC DIVISION CIRCUIT; SYSTOLIC DIVISION CIRCUIT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036287913     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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