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Volumn 4, Issue , 2001, Pages 80-83

A 1.25 GHz 32-bit tree-structured carry lookahead adder

Author keywords

[No Author keywords available]

Indexed keywords

ALL N TRANSISTORS; CARRY LOOKAHEAD ADDER; POST LAYOUT SIMULATION; PROPOSED ARCHITECTURES; SMALL AREA; TRANSISTOR COUNT; TREE-STRUCTURED;

EID: 0013016056     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922174     Document Type: Conference Paper
Times cited : (15)

References (9)
  • 2
    • 0024611252 scopus 로고
    • High-speed CMOS circuit technique
    • Feb
    • J. Yuan., and C. Svensson, "High-speed CMOS circuit technique" IEEE J. Solid-State Circuits, vol. 24, pp. 62-70. Feb. 1989.
    • (1989) IEEE J. Solid-State Circuits , vol.24 , pp. 62-70
    • Yuan, J.1    Svensson, C.2
  • 4
    • 0030110217 scopus 로고    scopus 로고
    • An 800-MHz 1mm CMOS pipelined 8-b adder using true single phase clocked logic-flip-flops
    • Mar
    • R. Rogenmoser, and Q. Huang, "An 800-MHz 1mm CMOS pipelined 8-b adder using true single phase clocked logic-flip-flops." IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 401-409, Mar. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , Issue.3 , pp. 401-409
    • Rogenmoser, R.1    Huang, Q.2
  • 5
    • 0030084589 scopus 로고    scopus 로고
    • All-N-logic highspeed true-single-phase dynamic CMOS logic
    • Feb
    • R. X. Gu, and M. I. Elmasry, "All-N-logic highspeed true-single-phase dynamic CMOS logic," IEEE J. Solid-State Circuits, vol. 31, no. 2, pp. 221-229, Feb. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , Issue.2 , pp. 221-229
    • Gu, R.X.1    Elmasry, M.I.2
  • 6
    • 0030082972 scopus 로고    scopus 로고
    • A robust single phase clocking for low power high-speed VLSI application
    • Feb
    • M. Afghahi, "A robust single phase clocking for low power high-speed VLSI application," IEEE J. Solid-State Circuits, vol. 31, no. 2, pp. 247-253, Feb. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , Issue.2 , pp. 247-253
    • Afghahi, M.1
  • 9
    • 0020102009 scopus 로고
    • A regular layout for parallel adders
    • Mar
    • R. P. Brent, and H. T. Kung, "A regular layout for parallel adders," IEEE Trans. Computers, vol. C-31, no. 3. pp. 260-264, Mar. 1982.
    • (1982) IEEE Trans. Computers , vol.C-31 , Issue.3 , pp. 260-264
    • Brent, R.P.1    Kung, H.T.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.