-
1
-
-
0031075756
-
Fast adders using enhanced multiple-output domino logic
-
Feb
-
Z. Wang, G. A. Jullien. W. C. Miller, J. Wang, and S. S. Bizzan, "Fast adders using enhanced multiple-output domino logic." IEEE J. Solid-State Circuits, vol. 32, no. 2, pp. 206-214, Feb. 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, Issue.2
, pp. 206-214
-
-
Wang, Z.1
Jullien, G.A.2
Miller, W.C.3
Wang, J.4
Bizzan, S.S.5
-
2
-
-
0024611252
-
High-speed CMOS circuit technique
-
Feb
-
J. Yuan., and C. Svensson, "High-speed CMOS circuit technique" IEEE J. Solid-State Circuits, vol. 24, pp. 62-70. Feb. 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 62-70
-
-
Yuan, J.1
Svensson, C.2
-
4
-
-
0030110217
-
An 800-MHz 1mm CMOS pipelined 8-b adder using true single phase clocked logic-flip-flops
-
Mar
-
R. Rogenmoser, and Q. Huang, "An 800-MHz 1mm CMOS pipelined 8-b adder using true single phase clocked logic-flip-flops." IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 401-409, Mar. 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, Issue.3
, pp. 401-409
-
-
Rogenmoser, R.1
Huang, Q.2
-
5
-
-
0030084589
-
All-N-logic highspeed true-single-phase dynamic CMOS logic
-
Feb
-
R. X. Gu, and M. I. Elmasry, "All-N-logic highspeed true-single-phase dynamic CMOS logic," IEEE J. Solid-State Circuits, vol. 31, no. 2, pp. 221-229, Feb. 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, Issue.2
, pp. 221-229
-
-
Gu, R.X.1
Elmasry, M.I.2
-
6
-
-
0030082972
-
A robust single phase clocking for low power high-speed VLSI application
-
Feb
-
M. Afghahi, "A robust single phase clocking for low power high-speed VLSI application," IEEE J. Solid-State Circuits, vol. 31, no. 2, pp. 247-253, Feb. 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, Issue.2
, pp. 247-253
-
-
Afghahi, M.1
-
7
-
-
0033896703
-
A 1.0 GHz 0.6-fim 8-bit carry lookahead adder using PLA-styled all-N-transistor logic
-
Feb
-
C-C. Wang, C.-J. Huang, and K.-C. Tsai, " A 1.0 GHz 0.6-fim 8-bit carry lookahead adder using PLA-styled all-N-transistor logic," IEEE Trans. Circuits and Systems, Part II: Analog and Digital Signal Processing, vol. 47, no. 2, pp. 133-135, Feb. 2000.
-
(2000)
IEEE Trans. Circuits and Systems, Part II: Analog and Digital Signal Processing
, vol.47
, Issue.2
, pp. 133-135
-
-
Wang, C.-C.1
Huang, C.-J.2
Tsai, K.-C.3
-
8
-
-
0029696942
-
A 3.5 ns, 64 bit, carry-lookahead adder
-
June
-
D. Dozza, M. Gaddoni, and G. Baccarani, "A 3.5 ns, 64 bit, carry-lookahead adder," 1996 IEEE Inter. Symp. on Circuits and Systems, vol. II, pp. 297-300, June 1996.
-
(1996)
1996 IEEE Inter. Symp. on Circuits and Systems
, vol.2
, pp. 297-300
-
-
Dozza, D.1
Gaddoni, M.2
Baccarani, G.3
-
9
-
-
0020102009
-
A regular layout for parallel adders
-
Mar
-
R. P. Brent, and H. T. Kung, "A regular layout for parallel adders," IEEE Trans. Computers, vol. C-31, no. 3. pp. 260-264, Mar. 1982.
-
(1982)
IEEE Trans. Computers
, vol.C-31
, Issue.3
, pp. 260-264
-
-
Brent, R.P.1
Kung, H.T.2
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