On-chip characterization of interconnect parameters and time delay in 0.18 μm CMOS technology for ULSI circuit applications

IEEE Transactions on Electron Devices

Volumn 47, Issue 5, 2000, Pages 1073-1079

  Lee, Hi Deok ^a   Kim, Dae M ^b   Jang, Myoung Jun ^a  

^a Hynix Semiconductor Inc   (South Korea)

^b Pohang University of Science and Technology (POSTECH)   (South Korea)

Author keywords

Interconnect delay time; Interconnect parameters; Multilevel metallization; RC delay in 0.18 m CMOS technology

Indexed keywords

EID: 0242359079     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.841243     Document Type: Article

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