Looking at the materials and thermal alternatives for scaled, next-century VLSI/ULSI interconnects

IEEE Circuits and Devices Magazine

Volumn 11, Issue 1, 1995, Pages 16-21

  Oh, Soo Young ^a   Chang, Keh Jeng ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COPPER; DELAY CIRCUITS; DIELECTRIC MATERIALS; ELECTRIC WIRING; ELECTRONICS PACKAGING; LITHOGRAPHY; PERFORMANCE; PERMITTIVITY; RELIABILITY; ULSI CIRCUITS; VLSI CIRCUITS;

ELECTROMIGRATION RELIABILITY; INTEGRATED CIRCUITS INTERCONNECTS; INTERCONNECT MODELING; PLANARIZATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029209053     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/101.340307     Document Type: Article

References (3)

1. MICRO TECH 2000 Workshop Report, National Advisory Committee on Semiconductors, August, 1991.
2. R.H. Dennard et a]., “Design of ion implanted MOSFETs with Very Small Physical Dimensions,” IEEE Journal of Solid-Slate Circuits, Vol. SC-9, pp. 256-268, Oct. 1974.
3. T. Sakurai, “Approximation of Wiring Delay on MOSFET LSI,” IEEE Journal of Solid-State Circuits, pp. 418-426. August 1983.