-
1
-
-
33747834300
-
The evolution of solid state circuits: 1958-1992-20??
-
Feb.
-
J. D. Meindl, “The evolution of solid state circuits: 1958-1992-20??,” 1993 IEEE ISSCC Commemorative Suppl., pp. 23-26, Feb. 1993.
-
(1993)
1993 IEEE ISSCC Commemorative Suppl.
, pp. 23-26
-
-
Meindl, J.D.1
-
2
-
-
0002007506
-
Progress in digital integrated electronics
-
G. E. Moore, “Progress in digital integrated electronics,” IEEE IEDM Tech. Dig., pp. 11-13, 1975.
-
(1975)
IEEE IEDM Tech. Dig.
, pp. 11-13
-
-
Moore, G.E.1
-
3
-
-
0020879241
-
Theoretical, practical and analogical limits in ULSI
-
J. D. Meindl, “Theoretical, practical and analogical limits in ULSI,” IEEE IEDM Tech. Dig., pp. 8-13, 1983.
-
(1983)
IEEE IEDM Tech. Dig.
, pp. 8-13
-
-
Meindl, J.D.1
-
4
-
-
0000328287
-
Irreversibility and heat generation in the computing process
-
July
-
R. Landauer, “Irreversibility and heat generation in the computing process,” IBM J. Res. and Develop., vol. 5, no. 3, pp. 183-191, July 1961.
-
(1961)
IBM J. Res. and Develop.
, vol.5
, Issue.3
, pp. 183-191
-
-
Landauer, R.1
-
5
-
-
16444366591
-
Dissipation and noise immunity in computation and communication
-
Oct. 27
-
R. Landauer, “Dissipation and noise immunity in computation and communication, Nature, vol. 335, pp. 779-784, Oct. 27, 1988.
-
(1988)
Nature
, vol.335
, pp. 779-784
-
-
Landauer, R.1
-
8
-
-
84936905168
-
Low power/low voltage: Future needs and envisioned solutions
-
M. Degrauwe et al., “Low power/low voltage: Future needs and envisioned solutions,” 1994 IEEE ISSCC Dig. Papers, pp. 98-99.
-
(1994)
IEEE ISSCC Dig. Papers
, pp. 98-99
-
-
Degrauwe, M.1
-
9
-
-
0028599648
-
Semiconductor technology crises and challenges toward the year 2000
-
S. Kohyama, “Semiconductor technology crises and challenges toward the year 2000,” 1994 Symp. VLSI Tech. Dig. of Papers, pp. 5-8.
-
(1994)
Symp. VLSI Tech. Dig. of Papers
, pp. 5-8
-
-
Kohyama, S.1
-
10
-
-
0003801840
-
Prospects for low power microprocessor design
-
Napa, CA, Apr.
-
D. Singh, “Prospects for low power microprocessor design,” Proc. 1994 Int. Workshop on Low Power Design, Napa, CA, Apr. 1994, p. 1.
-
(1994)
Proc. 1994 Int. Workshop on Low Power Design
, pp. 1
-
-
Singh, D.1
-
11
-
-
0003870436
-
I-V microsystems-scaling on schedule for personal communications
-
Mar.
-
S. Molhi and P. Chatterjee, “I-V microsystems-scaling on schedule for personal communications,” IEEE Circ. and Devices, Mar. 1994, pp. 13-17.
-
(1994)
IEEE Circ. and Devices
, pp. 13-17
-
-
Molhi, S.1
Chatterjee, P.2
-
12
-
-
0026853681
-
Low-power CMOS digital design
-
Apr.
-
A. P. Chandrakasan, S. Sheng, and R. Brodersen, “Low-power CMOS digital design, IEEE J. Solid-State Circ., vol. 27, pp. 473-484, Apr. 1992.
-
(1992)
IEEE J. Solid-State Circ.
, vol.27
, pp. 473-484
-
-
Chandrakasan, A.P.1
Sheng, S.2
Brodersen, R.3
-
13
-
-
30244484300
-
Metal-oxide-semiconductor field effect devices for micropower logic circuitry
-
E. Keonjian, Ed. London/New York: Pergamon
-
G. Moore et al., “Metal-oxide-semiconductor field effect devices for micropower logic circuitry,” in Micropower Electronics, E. Keonjian, Ed. London/New York: Pergamon, 1964.
-
(1964)
Micropower Electronics
-
-
Moore, G.1
-
14
-
-
0015330654
-
Ion-implanted complementary MOS transistors in low-voltage circuits
-
Apr.
-
R. M. Swanson and J. D. Meindl, “Ion-implanted complementary MOS transistors in low-voltage circuits,” IEEE J. Solid-State Circ., vol. SC-7, pp. 146-152, Apr. 1972.
-
(1972)
IEEE J. Solid-State Circ.
, vol.SC-7
, pp. 146-152
-
-
Swanson, R.M.1
Meindl, J.D.2
-
15
-
-
0027940828
-
Low-power design: Ways to approach the limits
-
E. A. Vittoz, “Low-power design: Ways to approach the limits,” 1994 IEEE ISSCC Dig. Papers, pp. 14-18.
-
(1994)
IEEE ISSCC Dig. Papers
, pp. 14-18
-
-
Vittoz, E.A.1
-
16
-
-
84936895447
-
Implantable telemetry
-
W. I. Gay and J. E. Heavner, Eds. New York: Academic
-
J. D. Meindl et al., “Implantable telemetry,” in Methods of Animal Experimentation, vol. 7, W. I. Gay and J. E. Heavner, Eds. New York: Academic, 1986, pp. 37-112.
-
(1986)
Methods of Animal Experimentation
, vol.7
, pp. 37-112
-
-
Meindl, J.D.1
-
17
-
-
0015331001
-
A monolithic micropower command receiver
-
Apr.
-
P. H. Hudson and J. D. Meindl, “A monolithic micropower command receiver,” IEEE J. Solid-State Circ., vol. SC-7, pp. 125-134, Apr. 1972.
-
(1972)
IEEE J. Solid-State Circ.
, vol.SC-7
, pp. 125-134
-
-
Hudson, P.H.1
Meindl, J.D.2
-
19
-
-
0016506999
-
Physical limits in digital electronics
-
May
-
R. W. Keyes, “Physical limits in digital electronics,” Proc. IEEE, vol. 63, pp. 740-766, May 1975.
-
(1975)
Proc. IEEE
, vol.63
, pp. 740-766
-
-
Keyes, R.W.1
-
20
-
-
0003391568
-
-
Reading, MA: Addison-Wesley
-
F. W. Sears, Thermodynamics. Reading, MA: Addison-Wesley, 1953.
-
(1953)
Thermodynamics.
-
-
Sears, F.W.1
-
22
-
-
84936905169
-
-
private communication
-
A. Bhavnagarwala, private communication.
-
-
-
Bhavnagarwala, A.1
-
23
-
-
0026121721
-
Monte carlo simulation of transport in technologically significant semiconductors-Part II: Submicrometer MOSFET's
-
Mar.
-
M. V. Fischetti and S. E. Laux, “Monte carlo simulation of transport in technologically significant semiconductors-Part II: Submicrometer MOSFET's,” IEEE Trans. Electron Devices, vol. 38, pp. 650-660, Mar. 1991.
-
(1991)
IEEE Trans. Electron Devices
, vol.38
, pp. 650-660
-
-
Fischetti, M.V.1
Laux, S.E.2
-
24
-
-
0027678066
-
Observation of velocity overshoot in silicon inversion layers
-
Oct.
-
F. Assaderaghi, “Observation of velocity overshoot in silicon inversion layers,” IEEE Electron Device Lett., vol. 14, pp. 484-486, Oct. 1993.
-
(1993)
IEEE Electron Device Lett.
, vol.14
, pp. 484-486
-
-
Assaderaghi, F.1
-
25
-
-
0021406605
-
Generalized scaling theory and its application to a 0.25 micron MOSFET
-
Apr.
-
G. Baccarani et al., “Generalized scaling theory and its application to a 0.25 micron MOSFET,” IEEE Trans. Electron Devices, vol. ED-31, pp. 452-470, Apr. 1984.
-
(1984)
IEEE Trans. Electron Devices
, vol.ED-31
, pp. 452-470
-
-
Baccarani, G.1
-
26
-
-
0020194040
-
Short channel MOSFET threshold voltage model
-
Oct.
-
K. N. Ratnakumer and J. Meindl, “Short channel MOSFET threshold voltage model,” IEEE J. Solid-State Circ., vol. SC-17, pp. 937-947, Oct. 1982.
-
(1982)
IEEE J. Solid-State Circ.
, vol.SC-17
, pp. 937-947
-
-
Ratnakumer, K.N.1
Meindl, J.2
-
27
-
-
0016113965
-
A simple theory to predict the threshold voltage of short channel IGFET's
-
L. D. Yau, “A simple theory to predict the threshold voltage of short channel IGFET's,” Solid-State Electron., vol. 17, pp. 1059-1063, 1974.
-
(1974)
Solid-State Electron.
, vol.17
, pp. 1059-1063
-
-
Yau, L.D.1
-
28
-
-
0018455052
-
VLSI limitations from drain induced barrier lowering
-
R. R. Troutman, “VLSI limitations from drain induced barrier lowering,” IEEE Trans. Electron Devices, vol. ED-26, pp. 461-469, 1979.
-
(1979)
IEEE Trans. Electron Devices
, vol.ED-26
, pp. 461-469
-
-
Troutman, R.R.1
-
29
-
-
84907697821
-
Opportunities for scaling MOSFET's for GSI
-
B. Agrawal, V. K. De, and J. D. Meindl, “Opportunities for scaling MOSFET's for GSI,” Proc. ESSDERC 1993, pp. 919-926.
-
(1993)
Proc. ESSDERC
, pp. 919-926
-
-
Agrawal, B.1
De, V.K.2
Meindl, J.D.3
-
30
-
-
84963965381
-
A new scaling method for 0.1-0.25 micron MOSFET
-
C. Fiegna et al., “A new scaling method for 0.1-0.25 micron MOSFET,” May 1993 Symp. VLSI Tech. Dig., pp. 33-34.
-
May 1993 Symp. VLSI Tech. Dig.
, pp. 33-34
-
-
Fiegna, C.1
-
31
-
-
0028459988
-
MOSFET scaling in the next decade and beyond
-
June
-
C. Hu, “MOSFET scaling in the next decade and beyond,” Semicon Int., June 1994, pp. 105-114.
-
(1994)
Semicon Int.
, pp. 105-114
-
-
Hu, C.1
-
32
-
-
0027878002
-
Sub-59nm gate length N-MOSFET's with 10nm phosphorous S/D junctions
-
M. Ono et al., “Sub-59nm gate length N-MOSFET's with 10nm phosphorous S/D junctions,” 1993 IEEE IEDM Tech. Dig., pp. 119-121.
-
(1993)
IEEE IEDM Tech. Dig.
, pp. 119-121
-
-
Ono, M.1
-
33
-
-
84954096367
-
Physics and technology of ultra short channel MOSFET's
-
D. A. Antoniades and J. E. Chung, “Physics and technology of ultra short channel MOSFET's,” 1991 IEEE IEDM Tech. Dig., pp. 21-24.
-
(1991)
IEEE IEDM Tech. Dig.
, pp. 21-24
-
-
Antoniades, D.A.1
Chung, J.E.2
-
34
-
-
0025212768
-
A fully depleted lean channel transistor (DELTA)-a novel vertical ultrathin SOI MOSFET
-
Jan.
-
D. Hisamoto et al., “A fully depleted lean channel transistor (DELTA)-a novel vertical ultrathin SOI MOSFET,” IEEE Electron Device Lett., vol. 11, pp. 36-38, Jan. 1990.
-
(1990)
IEEE Electron Device Lett.
, vol.11
, pp. 36-38
-
-
Hisamoto, D.1
-
35
-
-
85056911965
-
Monte Carlo simulation of a 30nm dual gate mosfet: How short can Si go?
-
D. J. Frank et al., “Monte Carlo simulation of a 30nm dual gate mosfet: How short can Si go?” 1992 IEEE IEDM Dig. Papers, pp. 553-556.
-
(1992)
IEEE IEDM Dig. Papers
, pp. 553-556
-
-
Frank, D.J.1
-
36
-
-
0028583847
-
Ultrafast low power operation of P+N+ double-gate SOI MOSFETs
-
T. Tanaka et al., “Ultrafast low power operation of P+N+ double-gate SOI MOSFETs,” 1994 Symp. VLSI Tech. Dig. of Papers, pp. 11-12.
-
(1994)
Symp. VLSI Tech. Dig. of Papers
, pp. 11-12
-
-
Tanaka, T.1
-
37
-
-
0024055902
-
An engineering model for short-channel MOS device
-
Aug.
-
K. Y. Toh et al., “An engineering model for short-channel MOS device,” IEEE J. Solid-State Circ., pp. 950-958, Aug. 1988.
-
(1988)
IEEE J. Solid-State Circ.
, pp. 950-958
-
-
Toh, K.Y.1
-
39
-
-
84936905170
-
-
private communication
-
J. Davis, private communication.
-
-
-
Davis, J.1
-
40
-
-
0026852420
-
Limitations, innovations and challenges of circuits and devices into a half micrometer and beyond
-
Apr.
-
M. Nagata, “Limitations, innovations and challenges of circuits and devices into a half micrometer and beyond,” IEEE J. Solid-State Circ., vol. 27, pp. 465-472, Apr. 1992.
-
(1992)
IEEE J. Solid-State Circ.
, vol.27
, pp. 465-472
-
-
Nagata, M.1
-
41
-
-
0026138627
-
An experimental 1.5v 64mb DRAM
-
Apr.
-
Y. Nakogame et al., “An experimental 1.5v 64mb DRAM,” IEEE J. Solid-State Circ., vol. 26, pp. 465-472, Apr. 1991.
-
(1991)
IEEE J. Solid-State Circ.
, vol.26
, pp. 465-472
-
-
Nakogame, Y.1
-
42
-
-
0026954548
-
A 1-V TFT-load SRAM using a two-step work-voltage method
-
Nov.
-
K. Ishibaski et al., “A 1-V TFT-load SRAM using a two-step work-voltage method,” IEEE J. Solid-State Circ., vol. 27, Nov. 1992.
-
(1992)
IEEE J. Solid-State Circ.
, vol.27
-
-
Ishibaski, K.1
-
43
-
-
0028465148
-
Subthreshold-current reduction circuits for multi-gigabit DRAM's
-
July
-
T. Sakata et al., “Subthreshold-current reduction circuits for multi-gigabit DRAM's,” IEEE J. Solid-State Circ., vol. 29, pp. 761-769, July 1994.
-
(1994)
IEEE J. Solid-State Circ.
, vol.29
, pp. 761-769
-
-
Sakata, T.1
-
44
-
-
0027577541
-
Low-voltage ULSI design
-
Apr.
-
K. Shimohigaski, “Low-voltage ULSI design,” IEEE J. Solid-State Circ., vol. 28, pp. 408-413, Apr. 1993.
-
(1993)
IEEE J. Solid-State Circ.
, vol.28
, pp. 408-413
-
-
Shimohigaski, K.1
-
45
-
-
0027575799
-
Sub-1-V swing internal bus architecture for future low-power ULSI's
-
Apr.
-
Y. Nakagome, “Sub-1-V swing internal bus architecture for future low-power ULSI's,” IEEE J. Solid-State Circ., vol. 28, pp. 414–419, Apr. 1993.
-
(1993)
IEEE J. Solid-State Circ.
, vol.28
, pp. 414-419
-
-
Nakagome, Y.1
-
46
-
-
0027879328
-
High performance 0.1 mm, CMOS devices with 1.5 V power supply
-
Dec.
-
Y. Taur et al., “High performance 0.1 mm, CMOS devices with 1.5 V power supply,” IEEE IEDM Tech. Dig., pp. 127-130, Dec. 1993.
-
(1993)
IEEE IEDM Tech. Dig.
, pp. 127-130
-
-
Taur, Y.1
-
47
-
-
84936892851
-
An ultra low-power 0.1 um CMOS
-
June
-
Y. Mu et al., “An ultra low-power 0.1 um CMOS,” Symp. VLSI Tech. Dig., pp. 9-10, June 1994.
-
(1994)
Symp. VLSI Tech. Dig.
, pp. 9-10
-
-
Mu, Y.1
-
48
-
-
0028134534
-
A 200 m V self-testing encoder/decoder using standard ultra-low power CMOS
-
Feb.
-
J. Burr and J. Shott, “A 200 m V self-testing encoder/decoder using standard ultra-low power CMOS,” IEEE ISSCC Dig., pp. 84-85, Feb. 1994.
-
(1994)
IEEE ISSCC Dig.
, pp. 84-85
-
-
Burr, J.1
Shott, J.2
-
49
-
-
0022061669
-
Optimal interconnection circuits for VLSI
-
May
-
H. B. Bakoglu and J. D. Meindl, “Optimal interconnection circuits for VLSI,” IEEE Trans. Electron Devices, vol. ED-37, pp. 903-909, May 1985.
-
(1985)
IEEE Trans. Electron Devices
, vol.ED-37
, pp. 903-909
-
-
Bakoglu, H.B.1
Meindl, J.D.2
-
50
-
-
0019923189
-
Why systolic architectures
-
Jan.
-
H. T. Kung, “Why systolic architectures,” IEEE Compu., pp. 37-46, Jan. 1982.
-
(1982)
IEEE Compu.
, pp. 37-46
-
-
Kung, H.T.1
-
51
-
-
84936895788
-
Systolic arrays—from concept to implementation
-
July
-
J. A. B. Fortes and B. W. Wah, “Systolic arrays—from concept to implementation,” IEEE Compu., pp. 12-17, July 1987.
-
(1987)
IEEE Compu.
, pp. 12-17
-
-
Fortes, J.A.B.1
Wah, B.W.2
-
52
-
-
84876370512
-
Computer architecture in the 1990's
-
Sept.
-
H. S. Stone and J. Cocke, “Computer architecture in the 1990's,” IEEE Compu., pp. 30-38, Sept. 1991.
-
(1991)
IEEE Compu.
, pp. 30-38
-
-
Stone, H.S.1
Cocke, J.2
-
53
-
-
0026914762
-
IBM enterprise system/9000 clock system: A technology and system perspective
-
Sept.
-
K. Chin et al., “IBM enterprise system/9000 clock system: A technology and system perspective,” IBM J. Res. Develop., vol. 37, no. 5, pp. 867-874, Sept. 1992.
-
(1992)
IBM J. Res. Develop.
, vol.37
, Issue.5
, pp. 867-874
-
-
Chin, K.1
-
54
-
-
0015206785
-
On a pin versus block relationship for partitioning of logic graphs
-
Dec.
-
B. S. Landrum and R. L. Russo, “On a pin versus block relationship for partitioning of logic graphs,” IEEE Trans. Compu., vol. C-20, pp. 1469-1479, Dec. 1971.
-
(1971)
IEEE Trans. Compu.
, vol.C-20
, pp. 1469-1479
-
-
Landrum, B.S.1
Russo, R.L.2
-
55
-
-
0018453798
-
Placement and average interconnection lengths of computer logic
-
Apr.
-
W. E. Donath, “Placement and average interconnection lengths of computer logic,” IEEE Trans. Circ. and Syst., vol. CAS-26, pp. 272-277, Apr. 1979.
-
(1979)
IEEE Trans. Circ. and Syst.
, vol.CAS-26
, pp. 272-277
-
-
Donath, W.E.1
-
56
-
-
0027659198
-
Possibilities of deep-submicrometer CMOS for very high speed computer logic
-
Sept.
-
A. Masaki, “Possibilities of deep-submicrometer CMOS for very high speed computer logic,” Proc. IEEE, vol. 81, pp. 1311-1324, Sept. 1993.
-
(1993)
Proc. IEEE
, vol.81
, pp. 1311-1324
-
-
Masaki, A.1
-
57
-
-
0038231353
-
High end processor trends and limits
-
Sendai, Japan Mar. 3-5
-
G. A. Sai-Halasz, “High end processor trends and limits,” Proc. Interconnect Conf. on Advanced Microelectron. Device Proc., Sendai, Japan, pp. 753-760, Mar. 3-5, 1994.
-
(1994)
Proc. Interconnect Conf. on Advanced Microelectron. Device Proc.
, pp. 753-760
-
-
Sai-Halasz, G.A.1
-
58
-
-
84936905171
-
-
private communication
-
J. C. Eble, private communication.
-
-
-
Eble, J.C.1
-
62
-
-
84936905173
-
-
private communication
-
V. De, private communication.
-
-
-
De, V.1
-
63
-
-
84972343753
-
Silicon valley, what next
-
July
-
C. R. Barrett, “Silicon valley, what next,” MRS Bull., pp. 3-10, July 1993.
-
(1993)
MRS Bull.
, pp. 3-10
-
-
Barrett, C.R.1
-
64
-
-
84936905174
-
National interests in a global semiconductor industry
-
Georgia Inst. of Technol., Atlanta, GA, Oct. 3
-
W. J. Spencer, “National interests in a global semiconductor industry,” Distinguished Lecturer Series, Georgia Inst. of Technol., Atlanta, GA, Oct. 3, 1994.
-
(1994)
Distinguished Lecturer Series
-
-
Spencer, W.J.1
|