-
2
-
-
0026400174
-
Possibilities of CMOS mainframe and its impact on technology R&D
-
A. Masaki, “Possibilities of CMOS mainframe and its impact on technology R&D,” Int. Symp. on VLSI Techn., p. 1, 1991.
-
(1991)
Int. Symp. on VLSI Techn.
, pp. 1
-
-
Masaki, A.1
-
3
-
-
0027659198
-
Possibilities of deep-submicrometer CMOS for very-high-speed computer logic
-
A. Masaki, “Possibilities of deep-submicrometer CMOS for very-high-speed computer logic,” Proc. IEEE, vol. 81, p. 1311, 1993.
-
(1993)
Proc. IEEE
, vol.81
, pp. 1311
-
-
Masaki, A.1
-
4
-
-
4243132732
-
A high performance 0.25 μm CMOS technology
-
B. Davari et al., “A high performance 0.25 μm CMOS technology,” IEDM Dig., p. 56, 1988.
-
(1988)
IEDM Dig.
, pp. 56
-
-
Davari, B.1
-
5
-
-
33646928144
-
Directions in future high-end processors
-
G. A. Sai-Halasz, “Directions in future high-end processors,” ICCD Dig., p. 230, 1992.
-
(1992)
ICCD Dig.
, pp. 230
-
-
Sai-Halasz, G.A.1
-
6
-
-
0026886276
-
Design of the IBM enterprise system/9000 high-end processors
-
J. S. Liptay, “Design of the IBM enterprise system/9000 high-end processors,” IBM J. Res. Develop., vol. 36, p. 713, 1992.
-
(1992)
IBM J. Res. Develop.
, vol.36
, pp. 713
-
-
Liptay, J.S.1
-
9
-
-
0015673515
-
Fully compensated emitter-coupled logic: eliminating the drawbacks of conventional ECL
-
H. H. Muller, W. K. Owens, and P. W. J. Verhofstadt, “Fully compensated emitter-coupled logic: eliminating the drawbacks of conventional ECL,” IEEE J. Solid-State Circ., vol. SC-8, p. 362, 1973.
-
(1973)
IEEE J. Solid-State Circ.
, vol.SC-8
, pp. 362
-
-
Muller, H.H.1
Owens, W.K.2
Verhofstadt, P.W.J.3
-
10
-
-
0026917451
-
Improved performance of IBM enterprise system/9000 bipolar logic chips
-
A. E. Barish, J. P. Eckhardt, M. D. Mayo, W. A. Swarczkopf, and S. P. Gaur, “Improved performance of IBM enterprise system/9000 bipolar logic chips,” IBM J. Res. Develop., vol. 36, p. 829, 1992.
-
(1992)
IBM J. Res. Develop.
, vol.36
, pp. 829
-
-
Barish, A.E.1
Eckhardt, J.P.2
Mayo, M.D.3
Swarczkopf, W.A.4
Gaur, S.P.5
-
11
-
-
0025487068
-
Figures of merit for system path time estimation
-
C. G. Hsi and S. G. Tucker, “Figures of merit for system path time estimation,” ICCD Dig., p. 49, 1990.
-
(1990)
ICCD Dig.
, pp. 49
-
-
Hsi, C.G.1
Tucker, S.G.2
-
12
-
-
33747363132
-
The need for low resistance interconnects in future high speed systems
-
P. Solomon, “The need for low resistance interconnects in future high speed systems,” Proc. SPIE vol. 947, p. 104, 1988.
-
(1988)
Proc. SPIE
, vol.947
, pp. 104
-
-
Solomon, P.1
-
13
-
-
0026888140
-
System cooling design for the inter-cooled IBM enterprise system/9000 processors
-
D. J. Delia et al., “System cooling design for the inter-cooled IBM enterprise system/9000 processors,” IBM J. Res. Develop., vol. 36, p. 791, 1992.
-
(1992)
IBM J. Res. Develop.
, vol.36
, pp. 791
-
-
Delia, D.J.1
-
14
-
-
0026888254
-
Three-loop feedback control of fault tolerant power supplies in IBM Enterprise System/9000 processors
-
K. B. Covi, “Three-loop feedback control of fault tolerant power supplies in IBM Enterprise System/9000 processors,” IBM J. Res. Develop., vol. 36, p. 781, 1992.
-
(1992)
IBM J. Res. Develop.
, vol.36
, pp. 781
-
-
Covi, K.B.1
-
16
-
-
0023539642
-
Opportunities for gigascale integration
-
J. D. Meindl, “Opportunities for gigascale integration,” Solid State Technol., vol. 30, p. 84, 1987.
-
(1987)
Solid State Technol.
, vol.30
, pp. 84
-
-
Meindl, J.D.1
-
17
-
-
0025799014
-
3-D capacitance modeling of advanced multilayer interconnection technologies
-
D. C. Edelstein, “3-D capacitance modeling of advanced multilayer interconnection technologies,” Proc. SPIE vol. 1389, p. 352, 1990.
-
(1990)
Proc. SPIE
, vol.1389
, pp. 352
-
-
Edelstein, D.C.1
-
19
-
-
0025452186
-
High speed signal propagation in lossy transmission lines
-
A. Deutsch et al., “High speed signal propagation in lossy transmission lines,” IBM J. Res. Develop., vol. 34, p. 601, 1990.
-
(1990)
IBM J. Res. Develop.
, vol.34
, pp. 601
-
-
Deutsch, A.1
-
20
-
-
0023363762
-
The fundamental limits for electronic packaging and systems
-
W. E. Pence and J. P. Krusius, “The fundamental limits for electronic packaging and systems,” IEEE Trans. Comp. Hybrid, Manuf. Technol., vol. CHMT-10, p. 176, 1987.
-
(1987)
IEEE Trans. Comp. Hybrid, Manuf. Technol.
, vol.CHMT-10
, pp. 176
-
-
Pence, W.E.1
Krusius, J.P.2
-
21
-
-
0018453798
-
Placement and average interconnection lengths of computer logic
-
W. E. Donath, “Placement and average interconnection lengths of computer logic,” IEEE Trans. Circ. and Syst., vol. CAS-26, p. 272, 1979.
-
(1979)
IEEE Trans. Circ. and Syst.
, vol.CAS-26
, pp. 272
-
-
Donath, W.E.1
-
22
-
-
0019565820
-
Wire length distribution for placements of computer logic
-
W. E. Donath, “Wire length distribution for placements of computer logic,” IBM J. Res. Develop., vol. 25, p. 152, 1981.
-
(1981)
IBM J. Res. Develop.
, vol.25
, pp. 152
-
-
Donath, W.E.1
-
23
-
-
0021481594
-
Wirability—Designing wiring space for chips and chip packages
-
W. R. Heller, C. G. Hsi, and W. F. Mikhaill, “Wirability—Designing wiring space for chips and chip packages,” IEEE Des. and Test. Comp., vol. 1, no. 3, p. 43, 1984.
-
(1984)
IEEE Des. and Test. Comp.
, vol.1
, Issue.3
, pp. 43
-
-
Heller, W.R.1
Hsi, C.G.2
Mikhaill, W.F.3
-
24
-
-
0025578482
-
HSST/BiCMOS technology with 26 ps ECL and 45 ps 2 V CMOS inverter
-
S. Konaka, T. Kobayashi, T. Matsuda, M. Ugajin, K. Imai, and T. Sakai, “HSST/BiCMOS technology with 26 ps ECL and 45 ps 2 V CMOS inverter,” IEDM Dig., p. 493, 1990.
-
(1990)
IEDM Dig.
, pp. 493
-
-
Konaka, S.1
Kobayashi, T.2
Matsuda, T.3
Ugajin, M.4
Imai, K.5
Sakai, T.6
-
25
-
-
84936894571
-
-
Order No. SH20-1118-0; available through IBM branch offices
-
ASTAP—Advanced Statistical Analysis Program, Order No. SH20-1118-0; available through IBM branch offices.
-
ASTAP—Advanced Statistical Analysis Program
-
-
-
26
-
-
0020125545
-
A comparison of semiconductor devices for high-speed logic
-
P. M. Solomon, “A comparison of semiconductor devices for high-speed logic,” Proc. IEEE, vol. 70, p. 489, 1982.
-
(1982)
Proc. IEEE
, vol.70
, pp. 489
-
-
Solomon, P.M.1
-
27
-
-
0024073264
-
High transconductance and velocity overshoot in NMOS devices at the 0.1 μm-gate-length level
-
G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, S. Rishton, and E. Ganin, “High transconductance and velocity overshoot in NMOS devices at the 0.1 μm-gate-length level,” IEEE Electron Device Lett., vol. 9, p. 464, 1988.
-
(1988)
IEEE Electron Device Lett.
, vol.9
, pp. 464
-
-
Sai-Halasz, G.A.1
Wordeman, M.R.2
Kern, D.P.3
Rishton, S.4
Ganin, E.5
-
28
-
-
0025455892
-
Experimental technology and performance of 0.1 μm-gate-length FETs operated at liquid-nitrogen temperature
-
G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, S. Rishton, E. Ganin, T. H. P. Chang, and R. H. Dennard, “Experimental technology and performance of 0.1 μm-gate-length FETs operated at liquid-nitrogen temperature,” IBM J. Res. Develop., vol. 34, p. 452, 1990.
-
(1990)
IBM J. Res. Develop.
, vol.34
, pp. 452
-
-
Sai-Halasz, G.A.1
Wordeman, M.R.2
Kern, D.P.3
Rishton, S.4
Ganin, E.5
Chang, T.H.P.6
Dennard, R.H.7
-
29
-
-
0026887482
-
Dual-tapered-piston (DPT) module cooling for the IBM Enterprise System/9000 systems
-
G. F. Goth, M. L. Zumbrunnen, and K. P. Moran, “Dual-tapered-piston (DPT) module cooling for the IBM Enterprise System/9000 systems,” IBM J. Res. Develop., vol. 36, p. 805, 1992.
-
(1992)
IBM J. Res. Develop.
, vol.36
, pp. 805
-
-
Goth, G.F.1
Zumbrunnen, M.L.2
Moran, K.P.3
-
31
-
-
0027168191
-
Reversible electronic logic using switches
-
R. C. Merkle, “Reversible electronic logic using switches,” Nanotechnology, vol. 4, p. 21, 1993.
-
(1993)
Nanotechnology
, vol.4
, pp. 21
-
-
Merkle, R.C.1
-
32
-
-
6044234792
-
Design of micron MOS switching devices
-
R. H. Dennard, F. H. Gaensslen, L. Kuhn, and H. N. Yu, “Design of micron MOS switching devices,” IEDM Dig., p. 344, 1972.
-
(1972)
IEDM Dig.
, pp. 344
-
-
Dennard, R.H.1
Gaensslen, F.H.2
Kuhn, L.3
Yu, H.N.4
-
33
-
-
0016116644
-
Design of ion-implanted MOSFETs with very small physical dimensions
-
R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. Le Blanc, “Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE J. Solid-State Circ., vol. SC-9, p. 256, 1974.
-
(1974)
IEEE J. Solid-State Circ.
, vol.SC-9
, pp. 256
-
-
Dennard, R.H.1
Gaensslen, F.H.2
Yu, H.N.3
Rideout, V.L.4
Bassous, E.5
Le Blanc, A.6
-
34
-
-
0021406605
-
Generalized scaling theory and its application to a 1/4 micrometer MOSFET design
-
G. Baccarani, M. R. Wordeman, and R. H. Dennard “Generalized scaling theory and its application to a 1/4 micrometer MOSFET design,” IEEE Trans. Electron Devices, vol. ED-31, p. 452, 1984.
-
(1984)
IEEE Trans. Electron Devices
, vol.ED-31
, pp. 452
-
-
Baccarani, G.1
Wordeman, M.R.2
Dennard, R.H.3
-
35
-
-
0015206785
-
On a pin or block relationship for partitions of logic graphs
-
B. S. Landman and R. L. Russo, “On a pin or block relationship for partitions of logic graphs,” IEEE Trans. Computers, vol. C-20, p. 1469, 1971.
-
(1971)
IEEE Trans. Computers
, vol.C-20
, pp. 1469
-
-
Landman, B.S.1
Russo, R.L.2
-
36
-
-
0016102199
-
Equivalence of memory to random logic
-
W. E. Donath, “Equivalence of memory to “random logic,” IBM J. Res. Develop., vol. 18, p. 401, 1974.
-
(1974)
IBM J. Res. Develop.
, vol.18
, pp. 401
-
-
Donath, W.E.1
-
37
-
-
33747946662
-
A 200 MHz 64b dual-issue CMOS microprocessor
-
D. Dobberpuhl et al., “A 200 MHz 64b dual-issue CMOS microprocessor,” ISSCC Dig. Tech. Papers, p. 106, 1992.
-
(1992)
ISSCC Dig. Tech. Papers
, pp. 106
-
-
Dobberpuhl, D.1
-
38
-
-
0026818953
-
A high speed superscaler PA-RISC processor
-
E. DeLano, W. Walker, J. Yetter, and M. Forsyth, “A high speed superscaler PA-RISC processor,” Dig. of Techn. Papers, Compcon, p. 116, 1992.
-
(1992)
Dig. of Techn. Papers, Compcon
, pp. 116
-
-
DeLano, E.1
Walker, W.2
Yetter, J.3
Forsyth, M.4
-
39
-
-
25344455160
-
Facet engineered elevated source/drain by selective Si epitaxy for 0.35 micron MOSFETs
-
C. Mazure, J. Fitch, and C. Gunderson, “Facet engineered elevated source/drain by selective Si epitaxy for 0.35 micron MOSFETs,” IEDM Dig., p. 853, 1992.
-
(1992)
IEDM Dig.
, pp. 853
-
-
Mazure, C.1
Fitch, J.2
Gunderson, C.3
-
40
-
-
84941448723
-
Design and experimental technology for 0.1 μm-gate-length low-temperature operation FET's
-
G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, E. Ganin, S. Rishton, D. S. Zicherman, H. Schmid, M. R. Polcari, H. Y. Ng, P. J. Restle, T. H. P. Chang, and R. H. Dennard, “Design and experimental technology for 0.1 μm-gate-length low-temperature operation FET's,” IEEE Electron Device Lett., vol. EDL-8, p. 463, 1987.
-
(1987)
IEEE Electron Device Lett.
, vol.EDL-8
, pp. 463
-
-
Sai-Halasz, G.A.1
Wordeman, M.R.2
Kern, D.P.3
Ganin, E.4
Rishton, S.5
Zicherman, D.S.6
Schmid, H.7
Polcari, M.R.8
Ng, H.Y.9
Restle, P.J.10
Chang, T.H.P.11
Dennard, R.H.12
-
41
-
-
0024140923
-
Inverter performance of deep submicron MOSFETs
-
G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, S. Rishton, E. Ganin, H. Y. Ng, D. Moy, T. H. P. Chang, and R. H. Dennard, “Inverter performance of deep submicron MOSFETs,” IEEE Electron Device Lett., vol. 9, p. 633, 1988.
-
(1988)
IEEE Electron Device Lett.
, vol.9
, pp. 633
-
-
Sai-Halasz, G.A.1
Wordeman, M.R.2
Kern, D.P.3
Rishton, S.4
Ganin, E.5
Ng, H.Y.6
Moy, D.7
Chang, T.H.P.8
Dennard, R.H.9
-
42
-
-
0005469038
-
High-performance 0.1 μm CMOS devices operating at room temperature
-
M. Iwase et al., “High-performance 0.1 μm CMOS devices operating at room temperature,” IEEE Electron Device Lett., vol. 14, p. 51, 1993.
-
(1993)
IEEE Electron Device Lett.
, vol.14
, pp. 51
-
-
Iwase, M.1
-
43
-
-
0027879328
-
High performance 0.1 μm CMOS devices with 1.5 V power supply
-
Y. Taur et al., “High performance 0.1 μm CMOS devices with 1.5 V power supply,” IEDM Dig., p. 127, 1993.
-
(1993)
IEDM Dig.
, pp. 127
-
-
Taur, Y.1
-
44
-
-
0027878002
-
Sub-50 nm gate-length N-MOSFETs with 10 nm phosphorus source and drain junctions
-
M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai, “Sub-50 nm gate-length N-MOSFETs with 10 nm phosphorus source and drain junctions,” IEDM Dig., p. 119, 1993.
-
(1993)
IEDM Dig.
, pp. 119
-
-
Ono, M.1
Saito, M.2
Yoshitomi, T.3
Fiegna, C.4
Ohguro, T.5
Iwai, H.6
-
45
-
-
0027845137
-
Room temperature 0.1 μm CMOS technology with 11.8 ps gate delay
-
K. F. Lee et al., “Room temperature 0.1 μm CMOS technology with 11.8 ps gate delay,” 1993 IEDM Dig., p. 131, 1993.
-
(1993)
1993 IEDM Dig.
, pp. 131
-
-
Lee, K.F.1
-
46
-
-
0017523140
-
A simple model for short channel MOSFET's
-
M. Fukuma and M. Matsumura, “A simple model for short channel MOSFET's,” Proc. IEEE, vol. 65, p. 1212, 1977.
-
(1977)
Proc. IEEE
, vol.65
, pp. 1212
-
-
Fukuma, M.1
Matsumura, M.2
-
47
-
-
0018545120
-
Geometry effects of small MOSFET devices
-
F. H. Gaensslen, “Geometry effects of small MOSFET devices,” IBM J. Res. Develop., vol. 23, p. 684, 1979.
-
(1979)
IBM J. Res. Develop.
, vol.23
, pp. 684
-
-
Gaensslen, F.H.1
-
48
-
-
0017466169
-
Very small MOSFETs for low temperature operation
-
F. H. Gaensslen, V. L. Rideout, E. J. Walker, and J. J. Walker, “Very small MOSFETs for low temperature operation,” IEEE Trans. Electron Devices, vol. ED-24, p. 218, 1977.
-
(1977)
IEEE Trans. Electron Devices
, vol.ED-24
, pp. 218
-
-
Gaensslen, F.H.1
Rideout, V.L.2
Walker, E.J.3
Walker, J.J.4
-
49
-
-
0000485237
-
SB-IGFET: an insulted gate FET using Schottky barrier contacts as source and drain
-
M. P. Lepselter and S. M. Sze, “SB-IGFET: an insulted gate FET using Schottky barrier contacts as source and drain,” Proc. IEEE, vol. 56, p. 1088, 1968.
-
(1968)
Proc. IEEE
, vol.56
, pp. 1088
-
-
Lepselter, M.P.1
Sze, S.M.2
-
51
-
-
84948608700
-
A room temperature 0.1 μm CMOS on SOI
-
G. G. Shahidi et al., “A room temperature 0.1 μm CMOS on SOI,” Int. Symp. on VLSI Tech., p. 27, 1993.
-
(1993)
Int. Symp. on VLSI Tech.
, pp. 27
-
-
Shahidi, G.G.1
-
52
-
-
0027867603
-
Optimization of series resistance in sub-0.2 μm SOI MOSFETs
-
L. T. Su, M. J. Shrnoy, H. Hu, J. E. Chung, and D. A. Antoniadis, “Optimization of series resistance in sub-0.2 μm SOI MOSFETs,” IEDM Dig., p. 723, 1993.
-
(1993)
IEDM Dig.
, pp. 723
-
-
Su, L.T.1
Shrnoy, M.J.2
Hu, H.3
Chung, J.E.4
Antoniadis, D.A.5
-
53
-
-
0027889411
-
SOI for a 1-Volt CMOS technology and application to a 512 Kb SRAM with 3.5 ns access time
-
G. G. Shahidi et al., “SOI for a 1-Volt CMOS technology and application to a 512 Kb SRAM with 3.5 ns access time,” IEDM Dig., p. 813, 1993.
-
(1993)
IEDM Dig.
, pp. 813
-
-
Shahidi, G.G.1
-
54
-
-
0027816874
-
High fmax; InA1As/InGaAs heterojunction bipolar transistors
-
H. F. Chau and Y. C. Kao, “High fmax; InA1As/InGaAs heterojunction bipolar transistors,” IEDM Dig., p. 783, 1993.
-
(1993)
IEDM Dig.
, pp. 783
-
-
Chau, H.F.1
Kao, Y.C.2
-
55
-
-
0024899805
-
SiGe heterojunction bipolar transistors
-
J. M. C. Stork, G. L. Patton, D. L. Harame, B. S. Meyerson, S. S. Iyer, E. Ganin, and E. F. Crabbé, “SiGe heterojunction bipolar transistors,” Int. Symp. on VLSI Tech., p. 1, 1991.
-
(1991)
Int. Symp. on VLSI Tech.
, pp. 1
-
-
Stork, J.M.C.1
Patton, G.L.2
Harame, D.L.3
Meyerson, B.S.4
Iyer, S.S.5
Ganin, E.6
Crabbé, E.F.7
-
56
-
-
0026121721
-
Monte Carlo simulation of transport in technologically significant semiconductors of the diamond and Zinc-Blende structure—Part II: Submicrometer MOSFETs
-
M. V. Fischetti and S. E. Laux, “Monte Carlo simulation of transport in technologically significant semiconductors of the diamond and Zinc-Blende structure—Part II: Submicrometer MOSFETs,” IEEE Trans. Electron Devices, vol. 38, p. 650, 1991.
-
(1991)
IEEE Trans. Electron Devices
, vol.38
, pp. 650
-
-
Fischetti, M.V.1
Laux, S.E.2
-
58
-
-
0023846621
-
Correlated discrete transfer of single electrons in ultra-small tunnel junctions
-
K. K. Likharev, “Correlated discrete transfer of single electrons in ultra-small tunnel junctions,” IBM J. Res. Develop., vol. 32, p. 144, 1988.
-
(1988)
IBM J. Res. Develop.
, vol.32
, pp. 144
-
-
Likharev, K.K.1
-
59
-
-
35949011620
-
Quantum optical Fredkin gate
-
G. J. Milburn, “Quantum optical Fredkin gate,” Phys. Rev. Lett., vol. 62, p. 2124, 1989.
-
(1989)
Phys. Rev. Lett.
, vol.62
, pp. 2124
-
-
Milburn, G.J.1
-
60
-
-
0003042819
-
Semiconductor Superlattices
-
L. Esaki and R. Tsu, “Semiconductor Superlattices,” IBM J. Res. Develop., vol. 14, p. 61, 1970.
-
(1970)
IBM J. Res. Develop.
, vol.14
, pp. 61
-
-
Esaki, L.1
Tsu, R.2
-
61
-
-
0018545753
-
Ballistic transport in semiconductor at low temperature for low-power high-speed logic
-
M. S. Shur and L. F. Eastman, “Ballistic transport in semiconductor at low temperature for low-power high-speed logic,” IEEE Trans. Electron Devices, vol. ED-26, p. 1677, 1979.
-
(1979)
IEEE Trans. Electron Devices
, vol.ED-26
, pp. 1677
-
-
Shur, M.S.1
Eastman, L.F.2
-
62
-
-
0018326846
-
Semiconductor Superlattices
-
B. L. H. Wilson, Ed. Bristol and London: The Institute of Physics, Conf. Series No. 43
-
G. A. Sai-Halasz, “Semiconductor Superlattices,” Physics of Semiconductors 1978, B. L. H. Wilson, Ed. Bristol and London: The Institute of Physics, Conf. Series No. 43, p. 21, 1979.
-
(1979)
Physics of Semiconductors 1978
, pp. 21
-
-
Sai-Halasz, G.A.1
-
63
-
-
0000464809
-
Tunneling hot-electron transfer amplifier: a hot electron GaAs device with current gain
-
M. Heiblum, D. C. Thomas, C. M. Knoedler, and M. I. Nathan, “Tunneling hot-electron transfer amplifier: a hot electron GaAs device with current gain,” Appl. Phys. Lett., vol. 47, p. 1105, 1985.
-
(1985)
Appl. Phys. Lett.
, vol.47
, pp. 1105
-
-
Heiblum, M.1
Thomas, D.C.2
Knoedler, C.M.3
Nathan, M.I.4
-
64
-
-
0011391329
-
Advanced technology and truth in advertising
-
R. Landauer, “Advanced technology and truth in advertising,” Physica A, vol. 168, p. 75, 1990.
-
(1990)
Physica A
, vol.168
, pp. 75
-
-
Landauer, R.1
-
65
-
-
0028269694
-
Envisioning a quantum supercomputer
-
S. Lloyd, “Envisioning a quantum supercomputer,” Science, vol. 263, p. 695, 1994.
-
(1994)
Science
, vol.263
, pp. 695
-
-
Lloyd, S.1
-
66
-
-
0024750508
-
Quantum functional devices: resonant-tunneling transistors, circuits with reduced complexity, and multiple-valued logic
-
F. Capasso, S. Sen, F. Beltram, L. M. Lundari, A. S. Vengurlekar, P. R. Smith, N. J. Shah, R. J. Malik, and A. Y. Cho, “Quantum functional devices: resonant-tunneling transistors, circuits with reduced complexity, and multiple-valued logic,” IEEE Trans. Electron Devices, vol. 36, p. 2065, 1989.
-
(1989)
IEEE Trans. Electron Devices
, vol.36
, pp. 2065
-
-
Capasso, F.1
Sen, S.2
Beltram, F.3
Lundari, L.M.4
Vengurlekar, A.S.5
Smith, P.R.6
Shah, N.J.7
Malik, R.J.8
Cho, A.Y.9
-
67
-
-
0027807140
-
Co-integrated resonant tunneling and heterojunction bipolar transistor full adder
-
A. C. Seabaugh, A. H. Taddiken, E. A. Beam, J. N. Randall, Y.-C. Kao, and B. Newell, “Co-integrated resonant tunneling and heterojunction bipolar transistor full adder,” IEDM Dig., p. 419, 1993.
-
(1993)
IEDM Dig.
, pp. 419
-
-
Seabaugh, A.C.1
Taddiken, A.H.2
Beam, E.A.3
Randall, J.N.4
Kao, Y.-C.5
Newell, B.6
-
68
-
-
85027173242
-
Real-time reconfigurable logic circuits using neuron MOS transistors
-
T. Shibata, K. Kotani, and T. Ohmi, “Real-time reconfigurable logic circuits using neuron MOS transistors,” ISSCC Dig. Tech. Papers, p. 238, 1993.
-
(1993)
ISSCC Dig. Tech. Papers
, pp. 238
-
-
Shibata, T.1
Kotani, K.2
Ohmi, T.3
|