Electrical test structure to evaluate linewidth variations due to proximity effects in optical lithography

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 1995, Pages 33-37

  Fallon, M ^a   Stevenson, J T M ^a   Walton, A J ^a   Gundlach, A M ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CORRELATION METHODS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC PROPERTIES; INTEGRATED CIRCUITS; MULTILAYERS; OPTIMIZATION; PHOTOLITHOGRAPHY; SCANNING ELECTRON MICROSCOPY; TESTING;

ELECTRICAL LINEWIDTH VARIATIONS; OPTICAL LITHOGRAPHY; PROXIMITY EFFECTS; TEST STRUCTURE; TOPOGRAPHICAL EDGES;

MICROELECTRONIC PROCESSING;

EID: 0029216579     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)