메뉴 건너뛰기




Volumn 2001-January, Issue , 2001, Pages 37-40

Testing FPGA delay faults in the system environment is very different from "ordinary"delay fault testing

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS;

EID: 0142194952     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/olt.2001.937815     Document Type: Conference Paper
Times cited : (11)

References (20)
  • 1
    • 0030652669 scopus 로고    scopus 로고
    • Test of ram-based FPGA: Methodology and application to the interconnect
    • M. Renovell, J. Figueras, Y. Zorian, "Test of RAM-based FPGA: Methodology and Application to the Interconnect", Proc. 15th VLSI Test Symp., pp. 230-237, 1997.
    • (1997) Proc. 15th VLSI Test Symp. , pp. 230-237
    • Renovell, M.1    Figueras, J.2    Zorian, Y.3
  • 5
    • 23044518418 scopus 로고    scopus 로고
    • A specific test methodology for symmetric SRAM-based FPGAS
    • R. W. Hartenstein, H. Grunbacher (eds.), Springer Verlag
    • M. Renovell, "A Specific Test Methodology for Symmetric SRAM-Based FPGAs", in R. W. Hartenstein, H. Grunbacher (eds.), Proc. 10'" Int. Conf. Field Programmable Logic and Applications, LNCS 1896, pp. 300-311, Springer Verlag, 2000.
    • (2000) Proc. 10' Int. Conf. Field Programmable Logic and Applications, LNCS , vol.1896 , pp. 300-311
    • Renovell, M.1
  • 6
    • 0029700620 scopus 로고    scopus 로고
    • Built-in self-test of logic blocks in FPGAS (finally, a free lunch: Bist without overhead!)
    • C. Stroud, S. Konala, P. Chen, M. Abramovici, "Built-in Self-Test of Logic Blocks in FPGAs (Finally, a Free Lunch: BIST Without Overhead!)", Proc. Nth VLSI Test Symp., pp. 387-392, 1996.
    • (1996) Proc. Nth VLSI Test Symp. , pp. 387-392
    • Stroud, C.1    Konala, S.2    Chen, P.3    Abramovici, M.4
  • 8
    • 0033335486 scopus 로고    scopus 로고
    • Using roving STARs for on-line testing and diagnosis of FPGAS in fault tolerant applications
    • M. Abramovici et al., "Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault Tolerant Applications", Proc. IEEE Int. Test Conf, pp. 973-982, 1999.
    • (1999) Proc. IEEE Int. Test Conf , pp. 973-982
    • Abramovici, M.1
  • 10
    • 84889013047 scopus 로고    scopus 로고
    • Application-dependent testing of FPGA delay faults
    • A. Krasniewski, "Application-Dependent Testing of FPGA Delay Faults", Proc. 25" EUROM1CRO Conf, vol. 1, pp. 260-267, 1999.
    • (1999) Proc. 25 EUROM1CRO Conf , vol.1 , pp. 260-267
    • Krasniewski, A.1
  • 11
    • 84879876156 scopus 로고    scopus 로고
    • Configuration self-test in FPGA-based reconfigurable systems
    • W. Quddus, A. Jas, N. A. Touba, "Configuration Self-Test in FPGA-Based Reconfigurable Systems", Proc. ISCAS'99, pp. 97100, 1999.
    • (1999) Proc. ISCAS'99 , pp. 97100
    • Quddus, W.1    Jas, A.2    Touba, N.A.3
  • 13
    • 84947589546 scopus 로고    scopus 로고
    • Exploiting reconfigurability for effective detection of delay faults in lut-based FPGAS
    • R. W. Hartenstein, H. Grunbacher (eds.), Springer Verlag
    • A. Krasniewski, "Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPGAs", in R. W. Hartenstein, H. Grunbacher (eds.), Proc. 10" Int. Conf. Field Programmable Logic and Applications, LNCS 1896, pp. 675684, Springer Verlag, 2000.
    • (2000) Proc. 10 Int. Conf. Field Programmable Logic and Applications, LNCS , vol.1896 , pp. 675684
    • Krasniewski, A.1
  • 14
    • 0041528983 scopus 로고    scopus 로고
    • Elimination of reconvergent fanouts in a network of luts for effective detection of FPGA delay faults
    • to be published
    • A. Krasniewski, "Elimination of Reconvergent Fanouts in a Network of LUTs for Effective Detection of FPGA Delay Faults", Proc. 4'" IEEE DDECS Workshop. 2001 (to be published).
    • (2001) Proc. 4' IEEE DDECS Workshop
    • Krasniewski, A.1
  • 15
    • 0027833796 scopus 로고
    • Delay testing for non-robust untestable circuits
    • K.-T. Cheng, H.-C. Chen, "Delay Testing for Non-Robust Untestable Circuits", Proc. IEEE Int'l Test Conf, pp. 954-961, 1993.
    • (1993) Proc. IEEE Int'l Test Conf , pp. 954-961
    • Cheng, K.-T.1    Chen, H.-C.2
  • 18
    • 0032652488 scopus 로고    scopus 로고
    • Primitive delay faults: Identification, testing, and design for testability
    • June
    • A. Krstic, K.-T. Cheng, S. T. Chakradhar, "Primitive Delay Faults: Identification, Testing, and Design for Testability", IEEE Trans, on CAD, pp. 669-684, June 1999.
    • (1999) IEEE Trans, on CAD , pp. 669-684
    • Krstic, A.1    Cheng, K.-T.2    Chakradhar, S.T.3
  • 20
    • 85042744406 scopus 로고    scopus 로고
    • Tech. Report, Institute of Telecommunications, Warsaw Univ. of Technology, Feb.
    • A. Krasniewski, Testability of Path Delay Faults in FPGAs, Tech. Report, Institute of Telecommunications, Warsaw Univ. of Technology, Feb. 2001.
    • (2001) Testability of Path Delay Faults in FPGAS
    • Krasniewski, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.