-
2
-
-
0029490526
-
A row-based fpga for single and multiple stuck-at fault detection
-
X. T. Chen,W. K. Huang, F. Lombardi, and X. Sun, "A Row-Based FPGA for Single and Multiple Stuck-At Fault Detection," in Proc. of IEEE Int. Work. on Defect and Fault Tolerance in VLSI Systems, pp. 225-233, 1995.
-
(1995)
Proc. of IEEE Int. Work. on Defect and Fault Tolerance in VLSI Systems
, pp. 225-233
-
-
Chen, X.T.1
Huang, W.K.2
Lombardi, F.3
Sun, X.4
-
3
-
-
0029700925
-
An approach for testing programmable/configurable field programmable gate arrays
-
W. K. Huang and F. Lombardi, "An Approach for Testing Programmable/Configurable Field Programmable Gate Arrays," in Proc. of IEEE VLSI Test Symp., pp. 450-455, 1996.
-
(1996)
Proc. of IEEE VLSI Test Symp.
, pp. 450-455
-
-
Huang, W.K.1
Lombardi, F.2
-
4
-
-
0029519091
-
Universal test complexity of field-programmable gate arrays
-
T. Inoue, H. Fujiwara, H. Michinishi, T. Yokohira, and T. Okamoto, "Universal Test Complexity of Field-Programmable Gate Arrays," in Proc. of Asian Test Symp., pp. 259-265, 1995.
-
(1995)
Proc. of Asian Test Symp.
, pp. 259-265
-
-
Inoue, T.1
Fujiwara, H.2
Michinishi, H.3
Yokohira, T.4
Okamoto, T.5
-
5
-
-
0029700620
-
Built-In self-test of logic blocks in fpgas
-
C. Stroud, P. Chen, and M. Abramovici, "Built-In Self-Test of Logic Blocks in FPGAs," in Proc. of IEEE VLSI Test Symp., pp. 387-392, 1996.
-
(1996)
Proc. of IEEE VLSI Test Symp.
, pp. 387-392
-
-
Stroud, C.1
Chen, P.2
Abramovici, M.3
-
7
-
-
0029710665
-
On the diagnosis of programmable interconnect systems: Theory and application
-
W. K. Huang, X. T. Chen, and F. Lombardi, "On the Diagnosis of Programmable Interconnect Systems: Theory and Application," in Proc. of IEEE VLSI Test Symp., pp. 204-209, 1996.
-
(1996)
Proc. of IEEE VLSI Test Symp.
, pp. 204-209
-
-
Huang, W.K.1
Chen, X.T.2
Lombardi, F.3
-
8
-
-
0141873644
-
BIST for clbs of a look-up table type fpga-A comparator based bist technique under definite fault models
-
N. Itazaki, Y. Matsumoto, and K. Kinoshita, "BIST for CLBs of a Look-Up Table Type FPGA-A Comparator Based BIST Technique under Definite Fault Models," in Proc. of 3rd IEEE Int. On-Line Testing Work., pp. 202-206, 1997.
-
(1997)
Proc. of 3rd IEEE Int. On-Line Testing Work.
, pp. 202-206
-
-
Itazaki, N.1
Matsumoto, Y.2
Kinoshita, K.3
-
9
-
-
0030652669
-
Test of rambased fpga: Methodology and application to the interconnect
-
M. Renovell, J. Figueras, and Y. Zorian, "Test of RAMBased FPGA: Methodology and Application to the Interconnect," in Proc. of IEEE VLSI Test Symp., pp. 230-237, 1997.
-
(1997)
Proc. of IEEE VLSI Test Symp.
, pp. 230-237
-
-
Renovell, M.1
Figueras, J.2
Zorian, Y.3
-
11
-
-
0030711195
-
A fpgabased implementation of a fault tolerant neural architecture for photon identification
-
M. Alderighi, E. Gummati, V. Piuri, and G. Sechi, "A FPGAbased Implementation of a Fault Tolerant Neural Architecture for Photon Identification," in fpga, pp. 166-172, 1997.
-
(1997)
Fpga
, pp. 166-172
-
-
Alderighi, M.1
Gummati, E.2
Piuri, V.3
Sechi, G.4
-
12
-
-
84893779586
-
Photon counting and analog intensified imagers for uv and x-ray radiation
-
E. G. Tanzi, "Photon Counting and Analog Intensified Imagers for UV and X-Ray Radiation," in IFCTR-CNR Tech. Rep., 1995.
-
(1995)
IFCTR-CNR Tech. Rep.
-
-
Tanzi, E.G.1
-
13
-
-
0030697724
-
-
S. DAngelo, L. Mantoani, R. Mazzei, S. Russo, and G. Sechi, "Modular design of communication node prototype," pp. 170-175, 1997.
-
(1997)
Modular Design of Communication Node Prototype
, pp. 170-175
-
-
Dangelo, S.1
Mantoani, L.2
Mazzei, R.3
Russo, S.4
Sechi, G.5
-
14
-
-
0007737292
-
Testing the interconnect strucutre of uncofigured ifpga
-
M. Renovell, J. Figueras, and Y. Zorian, "Testing the Interconnect Strucutre of Uncofigured IFPGA," in Proc. of IEEE European Test Work., pp. 125-129, 1996.
-
(1996)
Proc. of IEEE European Test Work.
, pp. 125-129
-
-
Renovell, M.1
Figueras, J.2
Zorian, Y.3
-
15
-
-
0030411716
-
A test methodology for interconnect structures of LUT-based FPGAs
-
H. Michinishi, T. Yokohira, T. Okamoto, T. Inoue, and H. Fujiwara, "A test methodology for interconnect structures of LUT-based FPGAs," in Proc. of Asian Test Symp., pp. 68-74, 1996.
-
(1996)
Proc. of Asian Test Symp.
, pp. 68-74
-
-
Michinishi, H.1
Yokohira, T.2
Okamoto, T.3
Inoue, T.4
Fujiwara, H.5
-
16
-
-
84893795003
-
BIST-Based diagnostic of fpga logic blocks
-
M. Abramovici, E. Lee, and C. Stroud, "BIST-Based Diagnostic of FPGA Logic Blocks," in Proc. of 3rd IEEE Int. On-Line Testing Work., pp. 196-201, 1997.
-
(1997)
Proc. of 3rd IEEE Int. On-Line Testing Work.
, pp. 196-201
-
-
Abramovici, M.1
Lee, E.2
Stroud, C.3
-
17
-
-
11544310189
-
CMOS checkers with testable bridging and transistor stuck-on faults
-
C.Metra, M. Favalli, P. Olivo, and B. Ricco, "CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults," in Proc. of IEEE Int. Test Conf., pp. 948-957, 1992.
-
(1992)
Proc. of IEEE Int. Test Conf.
, pp. 948-957
-
-
Metra, C.1
Favalli, M.2
Olivo, P.3
Ricco, B.4
-
18
-
-
0031175881
-
On-Line detection of bridging and delay faults in functional blocks of cmos self-checking circuits
-
C. Metra, M. Favalli, P. Olivo, and B. Ricco, "On-Line Detection of Bridging and Delay Faults in Functional Blocks of CMOS Self-Checking Circuits," to appear in IEEE Trans. on CAD.
-
IEEE Trans. on CAD
-
-
Metra, C.1
Favalli, M.2
Olivo, P.3
Ricco, B.4
|