Testing finite state machines based on a structural coverage metric

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 773-780

  Gören, Sezer ^a   Ferguson, F Joel ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; FAILURE ANALYSIS; FINITE AUTOMATA; NETWORK PROTOCOLS; NUMERICAL METHODS;

ASYNCHRONOUS LOGIC; FAULT COVERAGE ANALYSIS; FINITE STATE MACHINE; SYNCHRONOUS LOGIC;

COMPUTER TESTING;

EID: 0036444597     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. A.D. Friedman and P.R. Menon, Fault Detection in Digital Circuits. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1971.
2. G.J. Holzmann, Design and Validation of Protocols. Englewood Cliffs, NJ: Prentice-Hall, 1990.
3. D. Lee and M. Yannakakis, "Testing Finite-State Machines: State Identification and Verification," IEEE Trans. on Computers, vol. 43, no.3, March 1994.
4. M. Yao, A. Petrenko, and G.V. Bochmann, "A Structural Analysis Approach to the Evaluation of Fault Coverage for Protocol Conformance Testing," Proceedings of the 7th IFIP WG 6.1 International Conference on Formal Description Techniques, pp. 399-414, 1995.
5. S. G̈ren, F.J. Ferguson, "Checking Sequence Generation for Asynchronous Sequential Elements," Int. Test Conference, pp. 406-413, 1999.
6. E.F. Moore, "Gedanken-experiments on sequential machines," Automata Studies, Princeton, NJ: Princeton University Press, 1956, no.34, pp. 129-153.
7. F.C. Hennie, "Fault Detecting Experiments for Sequential Circuits," Int. Symp. on Swit. Circuit Theory and Logic Design, pp. 95-110, 1964.