Improving structural FSM traversal by constraint-satisfying logic simulation

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volumn 2002-January, Issue , 2002, Pages 151-158

  Wedler, M ^a   Stoffel, D ^a   Kunz, W ^a  

^a France   (Germany)

Author keywords

Binary decision diagrams; Boolean functions; Circuit simulation; Combinational circuits; Computational efficiency; Computational modeling; Data structures; Electronic design automation and methodology; Formal verification; Logic

Indexed keywords

ALGORITHMS; BINARY DECISION DIAGRAMS; BOOLEAN FUNCTIONS; CIRCUIT SIMULATION; COMBINATORIAL CIRCUITS; COMPUTATION THEORY; COMPUTATIONAL EFFICIENCY; COMPUTER AIDED DESIGN; DATA STRUCTURES; FORMAL VERIFICATION; VLSI CIRCUITS;

COMPUTATIONAL COSTS; COMPUTATIONAL MODEL; ELECTRONIC DESIGN AUTOMATION AND METHODOLOGIES; EQUIVALENT FUNCTIONS; LOGIC; RANDOM SIMULATION; SIMULATION TECHNIQUE; VERIFICATION TOOLS;

LOGIC CIRCUITS;

EID: 84948650869     PISSN: 21593469     EISSN: 21593477     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2002.1016889     Document Type: Conference Paper

References (16)

1. Per Bjesse and Koen Claessen. SAT-based verification without state space traversal. In Proc. Intl. Conference on Formal Methods in Computer-Aided Design (FMCAD-00), November 2000.
2. Daniel Brand. Verification of large synthesized designs. In Proc. Intl. Conf. on Computer-Aided Design (ICCAD-93), pages 534-537, 1993.
3. Randy Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, 35(8):677-691, August 1986.
4. Oliver Coudert, C. Berthet, and Jean-Christophe Madre. Verification of synchronous sequential machines based on symbolic execution. Lecture Notes on Computer Science, 407:365-373, June 1989.
5. H. Fujiwara and T. Shimono. FAN: A fanout-oriented test pattern generation algorithm. In Proc. IEEE International Symposium on Circuits and Systems, pages 671-674, June 1985.
6. S.Y. Huang, K.T. Cheng, K.C. Chen, and Uwe Gläser. An ATPG-based framework for verifying sequential equivalence. In Proc. Intl. Test Conference (ITC-96), 1996.
7. J. Jain, R. Mukherjee, and M. Fujita. Advanced verification techniques based on learning. In Proc. 32nd ACM/IEEE Design Automation Conference (DAC-95), pages 420-426, June 1995.
8. Andreas Kühlmann and Florian Krohm. Equivalence checking using cuts and heaps. In Proc. Design Automation Conference (DAC-97), pages 263-268, Nov. 1997.
9. Wolfgang Kunz. An efficient tool for logic verification based on recursive learning. In Proc. Intl. Conference on Computer-Aided Design (ICCAD-93), pages 538-543, Nov. 1993.
10. Wolfgang Kunz and Dominik Stoffel. Reasoning in Boolean Networks - Logic Synthesis and Verification Using Testing Techniques. Kluwer Academic Publishers, Boston, 1997.
11. Yusuke Matsunaga. An efficient equivalence checker for combinational circuits. In Proc. Design Automation Conference (DAC-96), pages 629-634, June 1996.
12. K.L. McMillan. Symbolic Model Checking. Kluwer Academic Publishers, Boston, 1993.
13. Subodh Reddy, Wolfgang Kunz, and Dhiraj Pradhan. A novel verification framework combining structural and OBDD methods in a synthesis environment. In Proc. Design Automation Conference (DAC-95), pages 414-419, June 1995.
14. Dominik Stoffel. Formal Verification of Sequential Circuits Using Reasoning Techniques. PhD thesis, Johann Wolfgang Goethe - Universität, Frankfurt am Main, Germany, http://www.em.informatik.unifrankfurt.de, 1999.
15. Dominik Stoffel and Wolfgang Kunz. Record & play: A structural fixed point iteration for sequential circuit verification. In Proc. Intl. Conference on Computer-Aided Design (ICCAD-97), pages 394-399, Nov 1997.
16. C.A.J. van Eijk. Sequential equivalence checking without state space traversal. In Proc. Conference on Design, Automation and Test in Europe (DATE-98), pages 618-623, Paris, France, March 1998.