Failure analysis of 6T SRAM on low-voltage and high-frequency operation

IEEE Transactions on Electron Devices

Volumn 50, Issue 5, 2003, Pages 1270-1276

  Ikeda, Shuji ^a   Yoshida, Yasuko ^a   Ishibashi, Koichiro ^b,c   Mitsui, Yasuhiro ^d  

^a Trecenti Technologies Inc   (Japan)

^b HITACHI LTD   (Japan)

^c STARC   (Japan)

^d HITACHI HIGH TECHNOLOGIES CORPORATION   (Japan)

Author keywords

Grain size (new); High speed integrated circuits; Hydrazine (new); Low voltage (new); Nanoprobe (new); Noise; SRAM chips; Stability

Indexed keywords

DEGRADATION; ETCHING; FAILURE ANALYSIS; FREQUENCIES; GATES (TRANSISTOR); HYDRAZINE; MOS DEVICES; POLYSILICON; RANDOM ACCESS STORAGE; SPURIOUS SIGNAL NOISE; THRESHOLD VOLTAGE; TRANSMISSION ELECTRON MICROSCOPY;

ACTUAL MEMORY CELLS; DRAIN CURRENT DEGRADATION; GATE DEPLETION; HIGH FREQUENCY OPERATION; STATIC RANDOM ACCESS MEMORY;

SEMICONDUCTOR DEVICE TESTING;

EID: 0043175220     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.813474     Document Type: Article

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