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Volumn 22, Issue 5, 1987, Pages 748-754

Static-Noise Margin Analysis of MOS SRAM Cells

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, DIGITAL - RANDOM ACCESS; SEMICONDUCTOR DEVICES, MOS;

EID: 0023437909     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1987.1052809     Document Type: Article
Times cited : (1160)

References (9)
  • 1
    • 0022247204 scopus 로고
    • Phase plane analysis of the upset characteristics of CMOS RAM cells
    • (Auburn, AL), June
    • R. C. Jaeger and R. M. Fox, “Phase plane analysis of the upset characteristics of CMOS RAM cells,” in Proc. Univ./Govt./Industry Microelectron. Symp. (Auburn, AL), June 1985, pp. 183–187.
    • (1985) Proc. Univ./Govt./Industry Microelectron. Symp , pp. 183-187
    • Jaeger, R.C.1    Fox, R.M.2
  • 2
    • 0019009609 scopus 로고
    • The behavior of flip-flops used as synchronizers and prediction of their failure rate
    • Apr.
    • H. J. M. Veendrick, “The behavior of flip-flops used as synchronizers and prediction of their failure rate,” IEEE J. Solid-State Circuits, vol. SC-15, no. 2, 169–176, Apr. 1980.
    • (1980) IEEE J. Solid-State Circuits , vol.SC-15 , Issue.2 , pp. 169-176
    • Veendrick, H.J.M.1
  • 3
    • 0023293285 scopus 로고
    • Analysis of metastable operation in RS CMOS flip-flops
    • Feb.
    • T. Kacprzak and A. Albicki, “Analysis of metastable operation in RS CMOS flip-flops,” IEEE J. Solid-State Circuits, vol. SC-22, no. 1, pp. 57–64, Feb. 1987.
    • (1987) IEEE J. Solid-State Circuits , vol.SC-22 , Issue.1 , pp. 57-64
    • Kacprzak, T.1    Albicki, A.2
  • 4
    • 0020906578 scopus 로고
    • Worst-case static noise margin criteria for logic circuits and their mathematical equivalence
    • Dec.
    • J. Lohstroh, E. Seevinck, and J. de Groot, “Worst-case static noise margin criteria for logic circuits and their mathematical equivalence,” IEEE J. Solid-State Circuits, vol. SC-18, no. 6, pp. 803–807, Dec. 1983.
    • (1983) IEEE J. Solid-State Circuits , vol.SC-18 , Issue.6 , pp. 803-807
    • Lohstroh, J.1    Seevinck, E.2    de Groot, J.3
  • 6
    • 0022008805 scopus 로고
    • Stability and SER analysis of static RAM cells
    • Feb.
    • B. Chappell, S. E. Schuster, and G. S. Sai-Halasz, “Stability and SER analysis of static RAM cells,” IEEE J. Solid-State Circuits, vol. SC-20, no. 1, pp. 383–390, Feb. 1985.
    • (1985) IEEE J. Solid-State Circuits , vol.SC-20 , Issue.1 , pp. 383-390
    • Chappell, B.1    Schuster, S.E.2    Sai-Halasz, G.S.3
  • 7
    • 0022941733 scopus 로고
    • The static noise margin of SRAM cells
    • (Delft, The Netherlands), Sept.
    • F. J. List, ”The static noise margin of SRAM cells,” in Dig. Tech. Papers, ESSCIRC (Delft, The Netherlands), Sept. 1986, pp. 16–18.
    • (1986) Dig. Tech. Papers, ESSCIRC , pp. 16-18
    • List, F.J.1
  • 8
    • 0022115426 scopus 로고
    • Ion-implanted thin polycrystalline-silicon high-value resistors for high-density poly-load static RAM applications
    • Sept.
    • T. Ohzone, M. Fukumoto, G. Fuse, A. Shinohara, S. Odanaka, and M. Sasago, “Ion-implanted thin polycrystalline-silicon high-value resistors for high-density poly-load static RAM applications,” IEEE Trans. Electron Devices, vol. ED-32, no. 9, pp. 1749–1756, Sept. 1985.
    • (1985) IEEE Trans. Electron Devices , vol.ED-32 , Issue.9 , pp. 1749-1756
    • Ohzone, T.1    Fukumoto, M.2    Fuse, G.3    Shinohara, A.4    Odanaka, S.5    Sasago, M.6
  • 9
    • 2342604350 scopus 로고
    • Noise margin and noise immunity in logic circuits
    • Apr.
    • C. F. Hill, “Noise margin and noise immunity in logic circuits,” Microelectron., vol. 1, pp. 16–21, Apr. 1968.
    • (1968) Microelectron , vol.1 , pp. 16-21
    • Hill, C.F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.