Enhanced negative substrate bias degradation in nMOSFETs with ultrathin plasma nitrided oxide

IEEE Electron Device Letters

Volumn 24, Issue 5, 2003, Pages 333-335

  Perng, Tsu Hsiu ^a   Chien, Chao Hsin ^b   Chen, Ching Wei ^a   Lin, Horng Chih ^b   Chang, Chun Yen ^a   Huang, Tiao Yuan ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

Author keywords

Paramagnetic electron trap; Plasma nitrided gate dielectric; Substrate hot electron

Indexed keywords

CARRIER CONCENTRATION; DEGRADATION; ELECTRON ENERGY LEVELS; ELECTRON TRAPS; GATES (TRANSISTOR); HOT CARRIERS; NITRIDING; PLASMA APPLICATIONS; RAPID THERMAL ANNEALING; SUBSTRATES; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

PARAMAGNETIC ELECTRON TRAP; SUBSTRATE HOT ELECTRON; ULTRATHIN PLASMA NITRIDED OXIDE;

MOSFET DEVICES;

EID: 0041672426     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2003.812556     Document Type: Article

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