Fault models and test generation for hardware-software covalidation

IEEE Design and Test of Computers

Volumn 20, Issue 4, 2003, Pages 40-47

  Harris, Ian G ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; COMPUTER SOFTWARE SELECTION AND EVALUATION; DATA FLOW ANALYSIS; FAILURE ANALYSIS; FINITE AUTOMATA; HIGH LEVEL LANGUAGES; LOGIC PROGRAMMING; OPTIMIZATION;

AUTOMATIC TEST GENERATION; CONSTRAIN LOGIC PROGRAMMING; CONTROL DATAFLOW GRAPH; FAULT MODELS; FINITE STATE MACHINES; HARDWARE-SOFTWARE COVALIDATION;

COMPUTER TESTING;

EID: 0041521040     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1214351     Document Type: Article

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