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Volumn 2001-January, Issue , 2001, Pages 9-13

Automatic validation of pipeline specifications

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL LINGUISTICS; COMPUTER SOFTWARE; DESIGN; PIPELINES; PROGRAM COMPILERS; SPECIFICATIONS;

EID: 0041779812     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2001.972800     Document Type: Conference Paper
Times cited : (8)

References (12)
  • 1
    • 84893597192 scopus 로고    scopus 로고
    • EXPRESSION: A language for architecture exploration through compiler/simulator retargetability
    • A. Halambi et al. EXPRESSION: A language for architecture exploration through compiler/simulator retargetability. In DATE, 1999.
    • (1999) DATE
    • Halambi, A.1
  • 2
    • 0030712735 scopus 로고    scopus 로고
    • ISDL: An instruction set description language for retargetability
    • G. Hadjiyiannis et al. ISDL: An instruction set description language for retargetability. In Proc. DAC, 1997.
    • (1997) Proc. DAC
    • Hadjiyiannis, G.1
  • 4
    • 84952844731 scopus 로고    scopus 로고
    • ARC Cores. http://www.arccores.com.
  • 6
    • 84952844732 scopus 로고    scopus 로고
    • Tensilica Incorporated. http://www.tensilica.com.
  • 7
    • 84952844733 scopus 로고    scopus 로고
    • Modeling and verification of processor pipelines in soc design exploration
    • H. Tomiyama et al. Modeling and verification of processor pipelines in soc design exploration. HLDVT, 1999.
    • (1999) HLDVT
    • Tomiyama, H.1
  • 8
    • 0030381152 scopus 로고    scopus 로고
    • LISA - Machine description language and generic machine model for HW/SW codesign
    • V. Zivojnovic et al. LISA - machine description language and generic machine model for HW/SW codesign. In VLSI Signal Processing, 1996.
    • (1996) VLSI Signal Processing
    • Zivojnovic, V.1
  • 9
    • 0003622047 scopus 로고    scopus 로고
    • http://www.trimaran.org. MDES User Manual, 1997.
    • (1997) MDES User Manual
  • 10
    • 0010823833 scopus 로고    scopus 로고
    • Verification of in-order execution in pipelined processors
    • H. Tomiyama et al. Verification of in-order execution in pipelined processors. HLDVT, 2000.
    • (2000) HLDVT
    • Tomiyama, H.1
  • 12
    • 84872256764 scopus 로고    scopus 로고
    • A processor description language supporting retargetable multi-pipeline dsp program development tools
    • Dec.
    • C. Siska. A processor description language supporting retargetable multi-pipeline dsp program development tools. In Proc. ISSS, Dec. 1998.
    • (1998) Proc. ISSS
    • Siska, C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.