Functional vector generation for HDL models using linear programming and 3-satisfiability

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 528-533

  Fallah, Farzan ^a   Devadas, Srinivas ^a   Keutzer, Kurt ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CIRCUITS; FORMAL LOGIC; FUNCTIONAL PROGRAMMING; LINEAR PROGRAMMING; ALGORITHMS; COMPUTER SIMULATION; DIGITAL ARITHMETIC; VECTORS;

AUTOMATIC GENERATION; LINEAR PROGRAMMING TECHNIQUES; LOGIC EQUATIONS; SATISFIABILITY CHECKING; SATISFIABILITY-CHECKING ALGORITHMS; SEAMLESS INTEGRATION; STATE OF THE ART; VECTOR GENERATION;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

CHECKING ALGORITHMS; SATISFIABILITY CHECKING METHODS;

EID: 0031638155     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/277044.277187     Document Type: Conference Paper

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