-
1
-
-
0029230835
-
Test program generation for functional verification of powerpc processors in ibm
-
A. Aharon, D. Goodman, M. Levinger, Y. Lichtenstein, Y. Malka, C. Metzger, M. Molcho, and G. Shurek. Test program generation for functional verification of powerpc processors in ibm. In 32nd Design Automation Conference, DAC 95, pages 279-285, 1995.
-
(1995)
32Nd Design Automation Conference, DAC 95
, pp. 279-285
-
-
Aharon, A.1
Goodman, D.2
Levinger, M.3
Lichtenstein, Y.4
Malka, Y.5
Metzger, C.6
Molcho, M.7
Shurek, G.8
-
3
-
-
84957635767
-
-
Technical Report 88.342, IBM Science and Technology, Haifa, Israel
-
I. Beer, M. Dvir, Kozitza B., Y. Lictenstein, S. Mack, W.J. Nee, Rappaport E., Schmierer Q., and Y. Zandman. VHDL Test Coverage in a BDLS/AUSSIM Environment. Technical Report 88.342, IBM Science and Technology, Haifa, Israel, 1993.
-
(1993)
VHDL Test Coverage in a BDLS/AUSSIM Environment
-
-
Beer, I.1
Dvir, M.2
Kozitza, B.3
Lictenstein, Y.4
Mack, S.5
Nee, W.J.6
Rappaport, E.7
Schmierer, Q.8
Zandman, Y.9
-
4
-
-
84987599101
-
Methodology and System for Practical Formal Verification of Reactive Hardware
-
I. Beer, M. Yoeli, S. Ben-David, R. Gewirtzman, and D. Geist. Methodology and System for Practical Formal Verification of Reactive Hardware. In Computer Aided Verification, pages 182-193, 1994.
-
(1994)
Computer Aided Verification
, pp. 182-193
-
-
Beer, I.1
Yoeli, M.2
Ben-David, S.3
Gewirtzman, R.4
Geist, D.5
-
6
-
-
0026986178
-
Validating Discrete Event Simulations Using Event Pattern Mappings
-
A. Benoit and D. Luckham. Validating Discrete Event Simulations Using Event Pattern Mappings. In ACM/IEEE Design Automation Conference, pages 414-419, 1992.
-
(1992)
ACM/IEEE Design Automation Conference
, pp. 414-419
-
-
Benoit, A.1
Luckham, D.2
-
7
-
-
0002147262
-
A theory for the derivation of tests
-
In S. Aggarwal and K Sabanni, editors, IFIP, North Holland
-
E. Brinksma. A theory for the derivation of tests. In S. Aggarwal and K Sabanni, editors, Protocol Specification, Testing, and Verification, IIIV, pages 119-131. IFIP, North Holland, 1988.
-
(1988)
Protocol Specification, Testing, and Verification, IIIV
, pp. 119-131
-
-
Brinksma, E.1
-
8
-
-
0022769976
-
Graph based algorithms for boolean function manipulation
-
R. E. Bryant. Graph based algorithms for boolean function manipulation. IEEE Trans. on Computers, C- 35, 1986.
-
(1986)
IEEE Trans. On Computers
, vol.35
-
-
Bryant, R.E.1
-
9
-
-
84863373723
-
The RNL Conformance Kit
-
In J. de Meet, L. Mackert, and W. Effelsberg, editors, North-Holland, October
-
S.P. van de Burgt, J. Kroon, E. Kwast, and H.J. Wilts. the RNL Conformance Kit. In J. de Meet, L. Mackert, and W. Effelsberg, editors, Proc. of the 2nd International Workshop on Protocol Test Systems, pages 279-294. North-Holland, October 1989.
-
(1989)
Proc. Of the 2Nd International Workshop on Protocol Test Systems
, pp. 279-294
-
-
Van De Burgt, S.P.1
Kroon, J.2
Kwast, E.3
Wilts, H.J.4
-
10
-
-
84957655603
-
On test sequence generation for protocols
-
In E. Brinksma, G Scollo, and C.A. Vissers, editors, IFIP, North Holland
-
W. Y.L Chan, S. T. Vuong, and M.R. Ito. On test sequence generation for protocols. In E. Brinksma, G Scollo, and C.A. Vissers, editors, Protocol Specification, Testing, and Verification,IX, pages 119-131. IFIP, North Holland, 1990.
-
(1990)
Protocol Specification, Testing, and Verification,Ix
, pp. 119-131
-
-
Chan, W.1
Vuong, S.T.2
Ito, M.R.3
-
11
-
-
0000574517
-
AVPGEN - A Test Case Generator for Architecture Verification
-
A. Chandra, V. Iyengar, D. Jameson, R. Jawalkelar, I. Nair, B. Rosen, M. Mullen, J. Yoon, R. Armoni, D. Geist, and Y. Wolfsthal. AVPGEN - A Test Case Generator for Architecture Verification. IEEE Transactions on VLSI Systems, 6(6), June 1995.
-
(1995)
IEEE Transactions on VLSI Systems
, vol.6
, Issue.6
-
-
Chandra, A.1
Iyengar, V.2
Jameson, D.3
Jawalkelar, R.4
Nair, I.5
Rosen, B.6
Mullen, M.7
Yoon, J.8
Armoni, R.9
Geist, D.10
Wolfsthal, Y.11
-
12
-
-
0029238629
-
Efficient generation of counter examples and witnesses in symbolic model checking
-
E. Clarke, O. Grumberg, K. Mcmillan, and X. Zhao. Efficient generation of counter examples and witnesses in symbolic model checking. 32rid ACM/IEEE Design Automation Conference, pages 427-432, 1995.
-
(1995)
32Rid ACM/IEEE Design Automation Conference
, pp. 427-432
-
-
Clarke, E.1
Grumberg, O.2
McMillan, K.3
Zhao, X.4
-
13
-
-
84957664000
-
SysGen Architecture Verification Program Generator User's Guide
-
Haifa, Israel, first edition
-
M. Farkas, D. Geist, and K. Holtz. SysGen Architecture Verification Program Generator User's Guide. IBM Science and Technology, Haifa, Israel, first edition, 1994.
-
(1994)
IBM Science and Technology
-
-
Farkas, M.1
Geist, D.2
Holtz, K.3
-
15
-
-
0029195606
-
Architecture validation for processors
-
R. C. Ho, C. H. Yang, M. A. Horowitz, and D. L. Dill. Architecture validation for processors. In International Symposium of Computer Architecture 1995, pages 404-413, 1995.
-
(1995)
International Symposium of Computer Architecture 1995
, pp. 404-413
-
-
Ho, R.C.1
Yang, C.H.2
Horowitz, M.A.3
Dill, D.L.4
-
20
-
-
0003928137
-
-
Carnegie Mellon University, Pittsburgh, PA
-
K. L. McMillan. The SMVSystem DRAFT. Carnegie Mellon University, Pittsburgh, PA, 1992.
-
(1992)
The Smvsystem DRAFT
-
-
McMillan, K.L.1
-
22
-
-
84957683925
-
-
PCI Special Interests Group, Portland, OR. PCI Local Bus Specification
-
PCI Special Interests Group, Portland, OR. PCI Local Bus Specification, 1995
-
(1995)
-
-
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