Cool-Fetch: Compiler-Enabled Power-Aware Fetch Throttling

IEEE Computer Architecture Letters

Volumn 1, Issue 1, 2002, Pages 5-

  Unsal, Osman S ^a   Koren, Israel ^a   Krishna, C Mani ^a   Moritz, Csaba Andras ^a  

^a University of Massachusetts   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0038702984     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2002.3     Document Type: Article

References (9)

1. Baniasadi A., Moshovos A., “Instruction Flow-Based Front-end Throttling for Power-Aware High-Performance Processors,” Proceedings of the International Symposium on Low Power Elec-tronics and Desian, ISLPED01 August 2001
2. Brooks D, Tiwari V., Martonosi M., “Wattch: A Framework for Architectural-Level Power Analysis and Optimizations,” Pro-ceedings of the 27th International Symposium on Computer Ar-chitecture, ISCA’00 June 2000
3. Cantin J. F., Hill M. D., “Cache Performance for Selected SPEC CPU2000 Benchmarks,” Computer Architecture News, Vol. 29, No. September 2001
4. Kever W., et al, “A 200MHz RISC Microprocessor with 128kB On-Chip Caches,” Proceedings of the International Solid-State Circuits Conference, ISSCC-97, February 1997
5. Sair S., Charney M., “Memory Behavior of the SPEC2000 Benchmark Suite,” IBM T. J. Watson Research Center Techni-cal Report, 2000
6. Tune E., Liang D., Tullsen D. M., Calder B., “Dynamic Pre-dictions of Critical Path Instructions,” 7th International Sym-posium on High Performance Computer Architecture, HPCA7, January 2001
7. Unsal O.S., Wang Z., Koren I., Krishna C.M., Moritz C.A., “On Memory Behavior of Scalars in Embedded Multimedia Systems,” Workshop on Memory Performance Issues, ISCA28, June 2001.
8. Unsal O.S., Ashok R., Koren I., Krishna C.M., Moritz C.A., “Cool-Cache for Hot Multimedia,” 34th Annual International Sumposium on Microarchitecture, MIC RO34, December 2001
9. Unsal O.S., Koren I., Krishna C.M., Moritz C.A., “The Minimax Cache: An Energy-Efficient Framework for Media Processors,” 8th International Symposium on High-Performance Computer Architecture, HPCA8, February 2002