Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 4, 2003, Pages 481-491

  Hrkic, Milos ^a   Lillis, John ^a  

^a University of Illinois at Chicago   (United States)

Author keywords

Buffer insertion; Routing; Steiner trees; Timing optimization

Indexed keywords

ALGORITHMS; CAPACITANCE; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; MATHEMATICAL MODELS; OPTIMIZATION; TOPOLOGY; VLSI CIRCUITS;

BUFFER INSERTION; BUFFER TREE SYNTHESIS; ROUTING; SINK POLARITY REQUIREMENTS; STEINER TREES; TEMPORAL LOCALITY;

INTEGRATED CIRCUIT LAYOUT;

EID: 0037390345     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.809648     Document Type: Article

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