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Volumn 19, Issue 2, 2000, Pages 234-241

Timing-driven maze routing

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; COMPUTER AIDED DESIGN; DYNAMIC PROGRAMMING; ELECTRIC RESISTANCE; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS;

EID: 0033877669     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.828552     Document Type: Article
Times cited : (20)

References (16)
  • 1
    • 84882536619 scopus 로고    scopus 로고
    • "An algorithm for path connection and its applications,"
    • 10, pp. 346-365, Sept. 1961
    • C. Y. Lee, "An algorithm for path connection and its applications," IRE Trans. Electron Comput., vol. EC-10, pp. 346-365, Sept. 1961.
    • IRE Trans. Electron Comput., Vol. EC
    • Lee, C.Y.1
  • 3
    • 0031634243 scopus 로고    scopus 로고
    • "Table-lookup methods for improved performancedriven routing," in
    • 35th DAC. 1998, pp. 368-377
    • J. Lillis and P. Buch, "Table-lookup methods for improved performancedriven routing," in Proc. 35th DAC. 1998, pp. 368-377.
    • Proc.
    • Lillis, J.1    Buch, P.2
  • 4
    • 0031642714 scopus 로고    scopus 로고
    • "Timing and crosstalk driven area routing," in
    • 35th DAC, 1998, pp. 378-381
    • H.-P. Tseng, L. Scheffer, and C. Sechen, "Timing and crosstalk driven area routing," in Proc. 35th DAC, 1998, pp. 378-381.
    • Proc.
    • Tseng, H.-P.1    Scheffer, L.2    Sechen, C.3
  • 5
    • 0030412696 scopus 로고    scopus 로고
    • "Post global routing crosstalk risk estimation and reduction," in
    • 1996, pp. 302-309
    • T. Xue, E. S. Kuh, and D. S. Wang, "Post global routing crosstalk risk estimation and reduction," in Proc. ICCAD, 1996, pp. 302-309.
    • Proc. ICCAD
    • Xue, T.1    Kuh, E.S.2    Wang, D.S.3
  • 6
    • 0031639541 scopus 로고    scopus 로고
    • "Global routing with crosstalk constraints," in
    • 35th DAC, 1998, pp. 374-377
    • H. Zhou and D. F. Wong, "Global routing with crosstalk constraints," in Proc. 35th DAC, 1998, pp. 374-377.
    • Proc.
    • Zhou, H.1    Wong, D.F.2
  • 7
    • 0023313404 scopus 로고    scopus 로고
    • "A simple yet effective technique for global wiring,"
    • 6, pp. 165-172, June 1987
    • R. Nair, "A simple yet effective technique for global wiring," IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 165-172, June 1987.
    • IEEE Trans. Computer-Aided Design, Vol. CAD
    • Nair, R.1
  • 10
    • 34748823693 scopus 로고    scopus 로고
    • "The transient response of damped linear network with particular regard to wideband amplifiers,"
    • vol. 19, pp. 55-63, 1948
    • W. C. Elmore, "The transient response of damped linear network with particular regard to wideband amplifiers," J. Appl. Phys., vol. 19, pp. 55-63, 1948.
    • J. Appl. Phys.
    • Elmore, W.C.1
  • 11
    • 0029488643 scopus 로고    scopus 로고
    • "Shaping a distributed-AC line to minimize Elmore delay,"
    • vol. 42, pp. 1020-1022, Dec. 1995
    • J. P. Fishburn and C. A. Schevon, "Shaping a distributed-AC line to minimize Elmore delay," IEEE Trans. Circuits Syst.-I, vol. 42, pp. 1020-1022, Dec. 1995.
    • IEEE Trans. Circuits Syst.-I
    • Fishburn, J.P.1    Schevon, C.A.2
  • 12
    • 0029698051 scopus 로고    scopus 로고
    • "Optimal wire-sizing formula under the Elmore delay model," in
    • 33rd DAC, 1996, pp. 487-490
    • C.-P. Chen, Y.-P. Chen, and D. F. Wong, "Optimal wire-sizing formula under the Elmore delay model," in Proc. 33rd DAC, 1996, pp. 487-490.
    • Proc.
    • Chen, C.-P.1    Chen, Y.-P.2    Wong, D.F.3
  • 13
    • 0031384628 scopus 로고    scopus 로고
    • "Delay bounded buffered tree construction for timing driven floorplanning," in
    • 1997, pp. 702-712
    • M. Kang, W.-M. Dai, T. Dillinger, and D. LaPotin, "Delay bounded buffered tree construction for timing driven floorplanning," in Proc. ICCAD, 1997, pp. 702-712.
    • Proc. ICCAD
    • Kang, M.1    Dai, W.-M.2    Dillinger, T.3    Lapotin, D.4
  • 14
    • 0030110490 scopus 로고    scopus 로고
    • "Optimal wire sizing and buffer insertion for low power and a generalized delay model,"
    • vol. 31, no. 3, pp. 437-447, 1996
    • J. Lillis, C.-K. Cheng, and T.-T. Y Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 437-447, 1996.
    • IEEE J. Solid-State Circuits
    • Lillis, J.1    Cheng, C.-K.2    Lin, T.-T.Y.3
  • 15
    • 0032668895 scopus 로고    scopus 로고
    • "Simultaneous routing and buffer insertion with restrictions on buffer locations," in
    • 36th DAC, 1999, pp. 96-99
    • H. Zhou, D. F. Wong, I.-M. Liu, and A. Aziz, "Simultaneous routing and buffer insertion with restrictions on buffer locations," in Proc. 36th DAC, 1999, pp. 96-99.
    • Proc.
    • Zhou, H.1    Wong, D.F.2    Liu, I.-M.3    Aziz, A.4
  • 16
    • 0029712263 scopus 로고    scopus 로고
    • "New techniques for performance driven routing with explicit area/delay tradeoff and simultaneous wire sizing," in
    • 1996, pp. 395-400
    • J. Lillis, C.-K. Cheng, T.-T. Y. Lin, and C.-Y. Ho, "New techniques for performance driven routing with explicit area/delay tradeoff and simultaneous wire sizing," in Proc. 33rd ACM/IEEE DAC, 1996, pp. 395-400.
    • Proc. 33rd ACM/IEEE DAC
    • Lillis, J.1    Cheng, C.-K.2    Lin, T.-T.Y.3    Ho, C.-Y.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.