Instruction-based self-testing of processor cores

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 19, Issue 2, 2003, Pages 103-112

  Kranitis, Nektarios ^a   Paschalis, Antonis ^a   Gizopoulos, Dimitris ^b   Zorian, Yervant ^c  

^a UNIVERSITY OF ATHENS   (Greece)

^b UNIVERSITY OF PIRAEUS   (Greece)

^c Virage Logic   (United States)

Author keywords

At speed testing; Built in self test; Instruction set; Processor cores; Software based self test

Indexed keywords

AUTOMATIC TESTING; BUILT-IN SELF TEST; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SOFTWARE; DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS; FAILURE ANALYSIS; MICROPROCESSOR CHIPS; REDUCED INSTRUCTION SET COMPUTING;

EMBEDDED PROCESSOR; INSTRUCTION SET ARCHITECTURE; REGISTER TRANSFER LEVEL; SYSTEMS-ON-CHIP;

INTEGRATED CIRCUIT TESTING;

EID: 0037377908     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1022873120308     Document Type: Article

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