An effective deterministic BIST scheme for shifter/accumulator pairs in datapaths

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 17, Issue 2, 2001, Pages 97-107

  Kranitis, Nektarios ^a   Paschalis, Antonis ^a   Gizopoulos, Dimitris ^b   Psarakis, Mihalis ^a   Zorian, Yervant ^c  

^a UNIVERSITY OF ATHENS   (Greece)

^b UNIVERSITY OF PIRAEUS   (Greece)

^c LogicVision Inc   (United States)

Author keywords

Accumulator; Arithmetic logic unit; Built in self test; Datapath test; Processor test; Shifter

Indexed keywords

ADDERS; DIGITAL SIGNAL PROCESSING; MICROPROCESSOR CHIPS; MULTIPLYING CIRCUITS; SHIFT REGISTERS;

ACCUMULATOR; ARITHMETIC LOGIC UNIT; DATAPATH TEST; SHIFTER-ACCUMULATOR PAIR;

BUILT-IN SELF TEST;

EID: 0035299582     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1011113508662     Document Type: Article

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