Automatic interconnection rectification for SoC design verification based on the port order fault model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 1, 2003, Pages 104-114

  Wang, Chun Yao ^a   Tung, Shing Wu ^a   Jou, Jing Yang ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Automatic interconnection rectification (AIR); Characteristic vector (CV); Correction; Detection; Diagnosis; Port order fault (POF); System on a chip (SoC); Undetected port sequence (UPS); Verification

Indexed keywords

ELECTRIC CONNECTORS; ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS;

AUTOMATIC INTERCONNECTION RECTIFICATION (AIR);

SYSTEMS ANALYSIS;

EID: 0037230611     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.805723     Document Type: Article

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