A logical fault model for library coherence checking

Journal of Information Science and Engineering

Volumn 14, Issue 3, 1998, Pages 567-586

  Tung, Shing W U ^a,b,c,d,e   Jou, Jing Yang ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b Comp and Commun Laboratories ^*  (Taiwan)

^c NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^d INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^e IEEE   (Taiwan)

Author keywords

Cell Library; Coherence Checking; Fault Model; Port Order Fault (POF); Test Pattern Generation; Verification

Indexed keywords

LIBRARY COHERENCE CHECKING; PORT ORDER FAULT (POF) MODELS;

COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; MATHEMATICAL MODELS; VECTORS;

SUBROUTINES;

EID: 0032163043     PISSN: 10162364     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (5)

1. Miron Abramovici et al., "Digital systems testing and testable design," Computer Science Press, 1990, pp. 98.
2. Shing-Wu Tung, "Automatic function check for cell library development," The 7th VLSI Design/CAD Symposium, 1996, pp. 169-170.
3. Giovanni De Micheli, "Synthesis and optimization of digital circuits," McGRAW-HILL, 1994, pp. 76.
4. Kwang-Ting Cheng and Jing-Yang Jou, "A functional fault model for sequential machines," in IEEE Transactions of CAD, Vol. 11, No. 9, 1992, pp. 1065-1073.
5. Paul F. Dierker and William L. Voxman, "Discrete Mathematics," Harcourt Brace Jovanovich, 1986, pp. 168.