Fault-simulation based design error diagnosis for sequential circuits

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 632-637

  Huang, Shi Yu ^a   Cheng, Kwang Ting ^b   Chen, Kuang Chien ^c   Lu, Juin Yeu Joseph ^a  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

^b University of California   (United States)

^c Verplex Systems Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY DECISION DIAGRAMS; SEQUENTIAL CIRCUITS; TIMING CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; ERROR DETECTION;

BENCHMARK CIRCUIT; DESIGN ERRORS; ERROR MODEL; FAULT SIMULATION; INPUT SEQUENCE; INTERNAL SIGNALS; POTENTIAL ERRORS;

ERRORS; SEQUENTIAL CIRCUITS;

DESIGN ERROR DIAGNOSIS; FAULT SIMULATION;

EID: 0031643948     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

1. H. Al-Asaad and J. P. Hayes, "Design Verification via Simulation and Automatic Test Pattern Generation, " Proc. oflnt'l Conf. on Computer-Aided Design, pp. 174-180, Nov. 1995.
2. M. S. Abadir, J. Ferguson, and T. E. Kirkland, "Logic Design Verification via Test Generation, " IEEE Trans, on Computer, pp. 138-148, Jan. 1988.
3. R. E. Bryant, "Graph-based Algorithms for Boolean Function Manipulation, " IEEE Trans, on Computers, vol. C-35, pp. 667-691, Aug. 1986.
4. W.-T. Cheng and M.-L. Yu, "Differential Fault Simulation-A Fast Method Using Minimal Memory, " Proc. of Design Automation Conf, pp. 424-428, June 1989.
5. P. Y. Chung, Y. M Wang, and I. N. Hajj, "Logic design error diagnosis and correction", IEEE Transactions on VLSI Systems, vol. 2, no. 3, pp. 320-332, Sept. 1994.
6. M. Fujita, "Methods for Automatic Design Error Correction in Sequential Circuits, " Proc. of European Conf. on Design Automation, pp. 76-80, 1993.
7. S.-Y. Huang, K.-T. Cheng, K.-C. Chen, and D.-I. Cheng, "ErrorTracer: A Fault Simulation Based Approach to Design Error Diagnosis, " Proc. oflnt'l Test Conf, pp. 974-981, Nov. 1997.
8. F. Krohm, A. Kuehlmann, and A. Mets, The Use of Random Simulation in Formal Verification, " Proc. of lnt'l Conf. on Computer Design, Oct. 1996.
9. A. Kuehlmann, D. I. Cheng, A. Srinivasan, and D. P. LaPo-tin, "Error Diagnosis for Transistor-level verification, " Proc. of Design Automation Conf, pp. 218-224, June 1994.
10. S. Y. Kuo, "Locating Logic Design Errors via Test Generation and Don't-Care Propagation, " Proc. of European Design Automation Conf, pp. 466-471, Sept. 1992.
11. H.-T. Liaw, J.-H. Tsaih, and C.-S. Lin, "Efficient Automatic Diagnosis of Digital Circuits", Proc. of lnt'l Conf. on Computer Aided Design, pp. 464-467, Nov. 1990.
12. C.-C. Lin, K.-C. Chen, S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, "Logic Synthesis for Engineering Change, " Proc. of Design Automation Conf pp. 647-652, June 1995.
13. J. C. Madre, O. Coudert, J. P. Billon, "Automating the Diagnosis and the Rectification of the Design Errors with PRIAM, " Proc. of Int'l Conf. on Computer Aided Design, pp. 30-33, Nov. 1989.
14. I. Pomeranz and S. M. Reddy, "On Correction of Multiple Design Errors, " IEEE Trans, of Computer-Aided Design of Integrated Circuits and Systems, pp. 255-264, vol. 14, no. 2, Feb. 1995.
15. I. Pomeranz and S. M. Reddy, "A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis, " Proc. of European Design Automation Conference, pp. 252-258, Sept. 1993.
16. "SIS: A System for Sequential Circuit Synthesis, " Report M92/41, University of California, Berkeley, 1992.
17. K. A. Tamura, "Locating Functional Errors in Logic Circuits, " Proc. of Design Automation Conference, pp. 185-191, June 1989.
18. M. Tomita, H. H. Jiang, T. Tomamoto, and Y. Hayashi, "An Algorithm for Locating Logic Design Errors, " Proc. of Int'l Conf. on Computer Aided Design, pp. 468-471, Nov. 1990.
19. A. G. Veneris and I. N. Hajj, "A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits, " Proc. of Great Lake Symposium on VLSI Design, pp. 45-50, March 1997.
20. A. M. Wahba and D. Borrione, "Design Error Diagnosis in Sequential Circuits, " Proc. of Correct Hardware Designs and Verification Methods, CHARME'95, Lecture Notes in Computer Science No. 987, pp. 171-188, Springer Verlag, Oct. 1995.
21. A. M. Wahba and D. Borrione, "A method for automatic design error location and correction in combinational logic circuits", Journal of Electronic Testing: Theory and Applica-tions, vol.8, no.2, pp. 113-27, April 1996.