Incremental logic rectification

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1997, Pages 143-149

  Huang, Shi Yu ^a   Chen, Kuang Chien ^a   Cheng, Kwang Ting ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ERROR DETECTION; LOGIC DESIGN; VECTORS;

LOGIC RECTIFICATION;

COMBINATORIAL CIRCUITS;

EID: 0030681122     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)