-
1
-
-
0023210698
-
DAGON: Technology binding and local optimization by DAG Matching
-
1987, pp. 341-347.
-
[1K. Keutzer, DAGON: Technology binding and local optimization by DAG Matching in Proc. 24th Design Autom. Conf., 1987, pp. 341-347.
-
Proc. 24th Design Autom. Conf.
-
-
Keutzer, K.1
-
2
-
-
0026998423
-
Characterization of Boolean functions for rapid matching in EPGA technology mapping
-
June 1992, pp. 374-379.
-
[2U. Schlichtmann, F. Brglez, and M. Hermann, Characterization of Boolean functions for rapid matching in EPGA technology mapping in Proc. 29th Design Autom. Conf., June 1992, pp. 374-379.
-
Proc. 29th Design Autom. Conf.
-
-
Schlichtmann, U.1
Brglez, F.2
Hermann, M.3
-
3
-
-
0004001585
-
-
Norwell, MA: Kluwer
-
[3S. D. Brown, R. J. Francis, J. Rose, and Z. G. Vranesic, FieldProgrammable Gate Arrays. Norwell, MA: Kluwer, 1992.
-
(1992)
FieldProgrammable Gate Arrays
-
-
Brown, S.D.1
Francis, R.J.2
Rose, J.3
Vranesic, Z.G.4
-
5
-
-
0024916005
-
Locating functional errors in logic circuits
-
1989, pp. 185-191.
-
[5K. A. Tamura, Locating functional errors in logic circuits in Proc. 26th Design Autom. Conf., 1989, pp. 185-191.
-
Proc. 26th Design Autom. Conf.
-
-
Tamura, K.A.1
-
9
-
-
0026962074
-
Locating logic design errors via test generation and don'tcare propagation
-
Sept. 1992, pp. 466-171.
-
[9S.-Y. Kuo, Locating logic design errors via test generation and don'tcare propagation 1992 Europ. Design-Autom. Conf., Sept. 1992, pp. 466-171.
-
1992 Europ. Design-Autom. Conf.
-
-
Kuo, S.-Y.1
-
10
-
-
84961257726
-
ACCORD: Automatic catching and correction of logic design errors in combinational circuits
-
1992, pp. 742-751.
-
[10P.-Y. Chung and I. N. Hajj, ACCORD: Automatic catching and correction of logic design errors in combinational circuits 1992 Int. Test Conf.. 1992, pp. 742-751.
-
1992 Int. Test Conf..
-
-
Chung, P.-Y.1
Hajj, I.N.2
-
14
-
-
33747061518
-
Test and diagnosis procedure for digital networks
-
Jan.
-
[14E. J. McCluskey, Test and diagnosis procedure for digital networks Computer, pp. 17-20, Jan. 1971.
-
(1971)
Computer
, pp. 17-20
-
-
McCluskey, E.J.1
-
15
-
-
0019030402
-
Multiple fault diagnosis in combinational circuits based on effect-cause analysis
-
pp. 451-60, June
-
[15M. Abramovici and M. A. Breuer, Multiple fault diagnosis in combinational circuits based on effect-cause analysis IEEE Trans. Comput., pp. 451-60, June 1980.
-
(1980)
IEEE Trans. Comput.
-
-
Abramovici, M.1
Breuer, M.A.2
-
16
-
-
0019213962
-
Fault dictionary compression: Recognizing when a fault may be unambiguously represented by a single failure detection
-
[16R. E. Tulloss, Fault dictionary compression: Recognizing when a fault may be unambiguously represented by a single failure detection 1980 Test Conf., pp. 368-370.
-
1980 Test Conf.
, pp. 368-370
-
-
Tulloss, R.E.1
-
19
-
-
0024053829
-
A method of fault analysis for test generation and fault diagnosis
-
July
-
[19H. Cox and J. Rajski, A method of fault analysis for test generation and fault diagnosis IEEE Trans. Computer-Aided Design, July 1988.
-
(1988)
IEEE Trans. Computer-Aided Design
-
-
Cox, H.1
Rajski, J.2
-
21
-
-
38749131846
-
Diagnosis oriented test pattern generation
-
Mar. 1990, pp. 470-474.
-
[21P. Camurati, A. Lioy, P. Prinetto, and M. Sonza Reorda, Diagnosis oriented test pattern generation Europ. Design Autom. Conf., Mar. 1990, pp. 470-474.
-
Europ. Design Autom. Conf.
-
-
Camurati, P.1
Lioy, A.2
Prinetto, P.3
Sonza Reorda, M.4
-
23
-
-
0026716871
-
Fault location with current monitoring
-
[23R. C. Aitken, Fault location with current monitoring in Proc. 1991 Int. Test Conf., pp. 623-632.
-
Proc. 1991 Int. Test Conf.
, pp. 623-632
-
-
Aitken, R.C.1
-
24
-
-
0026971356
-
Exact evaluation of diagnostic test resolution
-
June
-
[24K. Kubiak, S. Parkes, W. K. Fuchs, and R. Saleh, Exact evaluation of diagnostic test resolution 29th Design Autom. Conf, June 1992, pp. 347-352.
-
(1992)
29th Design Autom. Conf
, pp. 347-352
-
-
Kubiak, K.1
Parkes, S.2
Fuchs, W.K.3
Saleh, R.4
-
25
-
-
84961246518
-
Diagnostic fault simulation of sequential circuits
-
1992, pp. 178-186.
-
[25E. M. Rudnick, W. K. Fuchs, and J. H. Patel, Diagnostic fault simulation of sequential circuits Int. Test Conf., 1992, pp. 178-186.
-
Int. Test Conf.
-
-
Rudnick, E.M.1
Fuchs, W.K.2
Patel, J.H.3
-
27
-
-
0003567872
-
-
Nor-well, MA: Kluwer
-
[27R. Brayton, G. D. Hachtel, C. McMullen, and A. L. Sangiovanni- Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. Nor-well, MA: Kluwer, 1984.
-
(1984)
Logic Minimization Algorithms for VLSI Synthesis
-
-
Brayton, R.1
Hachtel, G.D.2
McMullen, C.3
Sangiovanni- Vincentelli, A.L.4
-
28
-
-
0028727437
-
Testability considerations in technology mapping
-
Nov.
-
[28I. Pomeranz and S. M. Reddy, Testability considerations in technology mapping in Proc. 3rd Asia Test Symp., Nov. 1994, pp. 151-156.
-
(1994)
Proc. 3rd Asia Test Symp.
, pp. 151-156
-
-
Pomeranz, I.1
Reddy, S.M.2
-
29
-
-
0030384473
-
Fault location based on circuit partitioning
-
Oct.
-
[29_, Fault location based on circuit partitioning in Proc. 1996 Int. Conf. on Computer Design, Oct. 1996, pp. 242-247.
-
(1996)
Proc. 1996 Int. Conf. on Computer Design
, pp. 242-247
-
-
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