On automatic-verification pattern generation for SoC with port-order fault model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 4, 2002, Pages 466-479

  Wang, Chun Yao ^a,b   Tung, Shing Wu ^a,b   Jou, Jing Yang ^a,b  

^a IEEE   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Automatic verification pattern generation (AVPG); Design verification; IEEE P1500; Port order fault (POF); SoC; Undetected port sequence (UPS)

Indexed keywords

PORT-ORDER FAULTS (POF);

ALGORITHMS; COMBINATORIAL CIRCUITS; EMBEDDED SYSTEMS; FLIP FLOP CIRCUITS; HEURISTIC METHODS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036539977     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.992770     Document Type: Article

References (16)

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