An improved AVPG algorithm for SoC design verification using port order fault model

Proceedings of the Asian Test Symposium

Volumn , Issue , 2001, Pages 431-436

  Wang, Chun Yao ^a   Tung, Shing Wu ^a   Jou, Jing Yang ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; FAILURE ANALYSIS; LOGIC DESIGN; MATHEMATICAL MODELS;

AUTOMATIC VERIFICATION PATTERN GENERATION; AUTOMORPHIC TECHNIQUE; PORT ORDER FAULT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035699193     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. A logic fault model for library coherence checking
2. Verification pattern generation for core-based design using port order fault model
3. An AVPG for SoC design verification with port order fault model
4. Surviving the SOC revolution - A guide to platform-based design
5. Interface-based design
6. Towards a standard for embedded core test: An example
7. Sequential circuit design using synthesis and optimization
8. A note on decision versus search for graph automorphism
9. On finding the number of graph automorphism