Transistor placement for noncomplementary digital VLSI cell synthesis

ACM Transactions on Design Automation of Electronic Systems

Volumn 8, Issue 1, 2003, Pages 81-107

  Riepe, Michael A ^a   Sakallah, Karem A ^b  

^a MAGMA DESIGN AUTOMATION   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Benchmark circuits; Cell Synthesis; Digital circuits; Euler graphs; Noncomplementary circuits; Sequence pair optimization; Transistor chaining; Transistor placement

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; SWITCHING CIRCUITS; TOPOLOGY; VLSI CIRCUITS;

CASCODE VOLTAGE SWITCH LOGIC (CVSL);

TRANSISTORS;

EID: 0037223225     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/606603.606608     Document Type: Article

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