A 286 MHz 64-b floating point multiplier with enhanced CG operation

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 4, 1996, Pages 504-512

  Makino, Hiroshi ^b,c,d,e   Suzuki, Hiroaki ^b   Morinaka, Hiroyuki ^b   Nakase, Yasunobu ^b   Mashiko, Koichiro ^a,b   Sumi, Tadashi ^b  

^a IEEE

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

^c KYOTO UNIVERSITY   (Japan)

^d System LSI Laboratory

^e TOHOKU UNIVERSITY

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER GRAPHICS; COMPUTER SOFTWARE; CRITICAL PATH ANALYSIS; LOGIC CIRCUITS; LOGIC GATES; MICROPROCESSOR CHIPS;

CRITICAL PATH DELAY; FLOATING POINT MULTIPLIER; REDUNDANT BINARY ARCHITECTURE; TRANSMISSION GATES;

MULTIPLYING CIRCUITS;

EID: 0030125293     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.499726     Document Type: Article

References (18)

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