AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 91-97

  Serdar, Tatjana ^a   Sechen, Carl ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; DIGITAL SIGNAL PROCESSING; ELECTRIC CONTACTS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; TRANSISTORS;

DIGITAL DATA PATH LAYOUT; PLACEMENT ALGORITHMS; WIRE CROSSOVERS;

COMPUTER AIDED DESIGN;

EID: 0033348304     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)