A two-dimensional transistor placement algorithm for cell synthesis and its application to standard cells

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E80-A, Issue 10, 1997, Pages 1883-1890

  Saika, Shunji ^a   Fukuui, Masahiro ^a   Shinomiya, Noriko ^b   Akino, Toshiro ^a   Kuninobu, Shigeo ^a  

^a PANASONIC CORPORATION   (Japan)

^b KINKI UNIVERSITY   (Japan)

Author keywords

Cell layout; Cell synthesis; Transistor placement; Twodimensional placement

Indexed keywords

ALGORITHMS; ELECTRIC WIRING; MATHEMATICAL MODELS; OPTIMIZATION; TRANSISTORS;

CELL LAYOUT; CELL SYNTHESIS; TWO DIMENSIONAL PLACEMENT ALGORITHM;

INTEGRATED CIRCUIT LAYOUT;

EID: 0031245664     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (11)

1. T. Uehara and W.M. VanCleemput, "Optimal layout of CMOS functional arrays," IEEE Trans. Comput., vol.30, pp.305-312, May 1981.
2. R.L. Maziasz and J.P. Hayes, "Layout optimization of static CMOS functional cells," IEEE Trans. Comput.Aided Des. Integrated Circuits & Syst., vol.9, no.7, July 1990.
3. S. Wimer, R.Y. Pinter, and J.A. Feldman, "Optimal chaining of CMOS transistors in a functional cell," IEEE Trans. Comput.-Aided Des. Integrated Circuits & Syst., vol.CAD6, no.5, Sept. 1987.
4. S. Rekhi, J.D. Trotter, and D.H. Linder, "Automatic layout synthesis of leaf cells," DAC, pp.267-272, 1995.
5. M. Lefebvre, C. Chan, and G. Martin, "Transistor placement and interconnect algorithms for leaf cell synthesis," EDAC, pp.119-123, 1990.
6. K. Tani, K. Izumi, M. Kashimura, T. Matsuda, and T. Fujii, "Two dimensional layout synthesis for large-scale CMOS circuits," ICC AD, pp.490-493, 1991.
7. D.G. Baltus and J. Alien, "SOLO: A generator of efficient layouts from optimized MOS circuit schematics," DAC, pp.445-452, 1988.
8. Y. Shiraishi, J. Sakemi, M. Kutsuwada, A. Tsukizoe, and T. Satoh, "A high packing density module generator for CMOS logic cells," DAC, pp.439-444, 1988.
9. T. Sadakane, H. Nakao, and M. Terai, "A new hierarchical algorithm for transistor placement in CMOS macro cell design," CICC, pp.461-464, 1995.
10. M. Fukui and T. Akino, "An algorithm for VLSI leaf cell generation," VLSI Design Tech., Report VLD94-65, Oct. 1994.
11. M. Fukui, N. Shinomiya, and T. Akino, "A new layout synthesis for leaf cell design," ASP-DAC, pp.259-264, 1995.