Fast adders using enhanced multiple-output domino logic

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 2, 1997, Pages 206-214

  Wang, Zhongde ^{a,b,c,f,g,h,i,j,k}   Jullien, Graham A ^{a,b,l,m,n,o,p}   Miller, William C ^a,b,q,r   Wang, Jinghong ^b,d,s,t,u   Bizzan, Sami S ^b,e  

^a IEEE   (Canada)

^b UNIVERSITY OF WINDSOR   (Canada)

^c Genesis Microchip Inc   (Canada)

^d NORTEL NETWORKS   (Canada)

^e ADVANCED MICRO DEVICES   (United States)

^f YUNNAN UNIVERSITY   (China)

^g KUNMING INSTITUTE OF PHYSICS   (China)

^h UNIVERSITY OF ARIZONA   (United States)

ⁱ BEIJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS   (China)

^j Chinese Institute of Electronics   (China)

^k American Mathematics Society   (United States)

^l LOUGHBOROUGH UNIVERSITY   (United Kingdom)

^m English Electric Computers ^*  (United Kingdom)

ⁿ EMI Ltd   (United Kingdom)

^o Advanced Photonic Systems Laboratory   (Canada)

^p Micronet Netwk Centers Excellence

^q UNIVERSITY OF MICHIGAN   (United States)

^r UNIVERSITY OF WATERLOO   (Canada)

^s TSINGHUA UNIVERSITY   (China)

^t Semiconductor Insights Inc Canada   (Canada)

^u Nothern Telecom Ltd   (Canada)

more..

Author keywords

Carry lookahead adders; CMOS logic; Domino logic; Sparse carry chains

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; CRITICAL PATH ANALYSIS; DELAY CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; MATHEMATICAL MODELS;

CARRY LOOKAHEAD ADDERS (CLA); SPARSE CARRY CHAINS;

ADDERS;

EID: 0031075756     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.551912     Document Type: Article

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