4.3ns 0.3μm CMOS 54×54b multiplier using precharged pass-transistor logic

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 364-365

  Hanawa, Makoto ^a   Kaneko, Kenji ^a   Kawashimo, Tatsuya ^a   Maruyama, Hiroshi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMPUTER SIMULATION; ENCODING (SYMBOLS); GATES (TRANSISTOR); LOGIC CIRCUITS; MOSFET DEVICES; MULTIPLYING CIRCUITS; REDUCED INSTRUCTION SET COMPUTING;

CARRY LOOKAHEAD ADDER; CARRY PROPAGATION ADDER; CRITICAL DELAY PATH; FLOATING POINT UNIT; PRECHARGED PASS TRANSISTOR CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0030081186     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)